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cmd/internal/obj/arm64: new arm64 assembling path for SVE

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This CL integrates a new assembling path specifically designed for SVE
and other modern ARM64 instructions, utilizing generated instruction
tables. It contains the foundational files and modifications to direct
the assembling pipeline to use this new data-driven path.

In a.out.go, it registers new constants for registers and operand types
used by SVE.

A new file inst.go is added, which defines the instruction table data
types and utility functions for the new path. The entry point from the
upstream pipeline is `tryEncode`.

`tryEncode` returns false upon an encoding failure, which allows the
upstream matching logic to handle multiple potential matches. The exact
match is not finalized until an instruction is actually encoded, as
detailed in the comments for `elemEncoders`.

This CL also introduces the core generated tables (`anames_gen.go`,
`encoding_gen.go`, `goops_gen.go`, and `inst_gen.go`) which handle a
wide variety of SVE instructions. A comprehensive end-to-end assembly
test file (`arm64sveenc.s`) is added, containing hundreds of test cases
for these SVE instructions to verify the new encoding path.

To facilitate these encodings, this CL implements handling for operand
types such as AC_ARNG, AC_PREG, AC_PREGZM, and AC_ZREG. Others are left
as TODOs.

The generated files in this CL are produced by the `instgen` tool in CL
755180.

Original author Eric Fang (eric.fang@arm.com, CL 424137)

Change-Id: I483f170c776fcd8edd8b8b04520f9d69ee0855dd
Reviewed-on: https://go-review.googlesource.com/c/go/+/742620
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
2026-02-04 17:19:04 +00:00
parent a45c8032bb
commit 79f3d38562
16 changed files with 9702 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/cmd/asm/internal/arch/arch.go
View File

@@ -275,6 +275,15 @@ func archArm64() *Arch {
for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := arm64.REG_Z0; i <= arm64.REG_Z31; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := arm64.REG_P0; i <= arm64.REG_P15; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := arm64.REG_PN0; i <= arm64.REG_PN15; i++ {
register[obj.Rconv(i)] = int16(i)
}
// System registers.
for i := 0; i < len(arm64.SystemReg); i++ {
@@ -292,9 +301,12 @@ func archArm64() *Arch {
delete(register, "R28")
register["g"] = arm64.REG_R28
registerPrefix := map[string]bool{
"F": true,
"R": true,
"V": true,
"F": true,
"R": true,
"V": true,
"Z": true,
"P": true,
"PN": true,
}
instructions := make(map[string]obj.As)

12
src/cmd/asm/internal/arch/arm64.go
View File

@@ -182,6 +182,18 @@ func arm64RegisterNumber(name string, n int16) (int16, bool) {
if 0 <= n && n <= 31 {
return arm64.REG_V0 + n, true
}
case "Z":
if 0 <= n && n <= 31 {
return arm64.REG_Z0 + n, true
}
case "P":
if 0 <= n && n <= 15 {
return arm64.REG_P0 + n, true
}
case "PN":
if 0 <= n && n <= 15 {
return arm64.REG_PN0 + n, true
}
}
return 0, false
}

31
src/cmd/asm/internal/asm/asm.go
View File

@@ -15,6 +15,7 @@ import (
"cmd/asm/internal/flags"
"cmd/asm/internal/lex"
"cmd/internal/obj"
"cmd/internal/obj/arm64"
"cmd/internal/obj/ppc64"
"cmd/internal/obj/riscv"
"cmd/internal/obj/x86"
@@ -593,6 +594,10 @@ func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) {
addr.Val = target
}
func isARM64SVE(op obj.As) bool {
return op > arm64.ASVESTART
}
// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
@@ -741,6 +746,11 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can
// not fit into prog.RegTo2, so save it to the prog.RestArgs.
prog.AddRestDest(a[2])
case isARM64SVE(op):
// SVE instructions, see arm64/goops_gen.go
prog.From = a[0]
prog.AddRestSource(a[1])
prog.To = a[2]
default:
prog.From = a[0]
prog.Reg = p.getRegister(prog, op, &a[1])
@@ -843,6 +853,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
break
}
if p.arch.Family == sys.ARM64 {
if isARM64SVE(op) {
// SVE instructions, see arm64/goops_gen.go
prog.From = a[0]
prog.AddRestSourceArgs([]obj.Addr{a[1], a[2]})
prog.To = a[3]
break
}
prog.From = a[0]
prog.Reg = p.getRegister(prog, op, &a[1])
prog.AddRestSource(a[2])
@@ -891,6 +908,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
p.errorf("can't handle %s instruction with 4 operands", op)
return
case 5:
if p.arch.Family == sys.ARM64 && isARM64SVE(op) {
// SVE instructions, see arm64/goops_gen.go
prog.From = a[0]
prog.AddRestSourceArgs([]obj.Addr{a[1], a[2], a[3]})
prog.To = a[4]
break
}
if p.arch.Family == sys.PPC64 {
prog.From = a[0]
// Second arg is always a register type on ppc64.
@@ -914,6 +938,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
p.errorf("can't handle %s instruction with 5 operands", op)
return
case 6:
if p.arch.Family == sys.ARM64 && isARM64SVE(op) {
// SVE instructions, see arm64/goops_gen.go
prog.From = a[0]
prog.AddRestSourceArgs([]obj.Addr{a[1], a[2], a[3], a[4]})
prog.To = a[5]
break
}
if p.arch.Family == sys.ARM && arch.IsARMMRC(op) {
// Strange special case: MCR, MRC.
prog.To.Type = obj.TYPE_CONST

8
src/cmd/asm/internal/asm/endtoend_test.go
View File

@@ -414,6 +414,14 @@ func TestARM64Encoder(t *testing.T) {
testEndToEnd(t, "arm64", "arm64enc")
}
func TestARM64SVEEncoder(t *testing.T) {
testEndToEnd(t, "arm64", "arm64sveenc")
}
func TestARM64SVEErrors(t *testing.T) {
testErrors(t, "arm64", "arm64sveerror")
}
func TestARM64Errors(t *testing.T) {
testErrors(t, "arm64", "arm64error")
}

582
src/cmd/asm/internal/asm/testdata/arm64sveenc.s vendored Normal file
View File

@@ -0,0 +1,582 @@
// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
#include "../../../../../runtime/textflag.h"
TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
PAND P4.B, P2.B, P1.Z, P14.B // 4e440425
PANDS P4.B, P2.B, P1.Z, P14.B // 4e444425
PBIC P4.B, P2.B, P1.Z, P14.B // 5e440425
PBICS P4.B, P2.B, P1.Z, P14.B // 5e444425
PBRKA P5.B, P9.Z, P2.B // a2641025
PBRKAS P5.B, P9.Z, P4.B // a4645025
PBRKB P5.B, P9.Z, P2.B // a2649025
PBRKBS P5.B, P9.Z, P4.B // a464d025
PBRKN P4.B, P2.B, P1.Z, P4.B // 44441825
PBRKNS P4.B, P2.B, P1.Z, P4.B // 44445825
PBRKPA P4.B, P2.B, P1.Z, P14.B // 4ec40425
PBRKPAS P4.B, P2.B, P1.Z, P14.B // 4ec44425
PBRKPB P4.B, P2.B, P1.Z, P14.B // 5ec40425
PBRKPBS P4.B, P2.B, P1.Z, P14.B // 5ec44425
PEOR P4.B, P2.B, P1.Z, P14.B // 4e460425
PEORS P4.B, P2.B, P1.Z, P14.B // 4e464425
PNAND P4.B, P2.B, P1.Z, P14.B // 5e468425
PNANDS P4.B, P2.B, P1.Z, P14.B // 5e46c425
PNOR P4.B, P2.B, P1.Z, P14.B // 4e468425
PNORS P4.B, P2.B, P1.Z, P14.B // 4e46c425
PORN P4.B, P2.B, P1.Z, P14.B // 5e448425
PORNS P4.B, P2.B, P1.Z, P14.B // 5e44c425
PORR P4.B, P2.B, P1.Z, P14.B // 4e448425
PORRS P4.B, P2.B, P1.Z, P14.B // 4e44c425
PPFALSE P13.B // 0de41825
PPFIRST P5.B, P9, P5.B // 25c15825
PPNEXT P5.D, P4, P5.D // 85c4d925
PPTEST P14.B, P0 // c0c15025
PPTRUE PN14.S // 1678a025
PPUNPKHI P14.B, P0.H // c0413105
PPUNPKLO P14.B, P0.H // c0413005
PRDFFR P13.B // 0df01925
PRDFFR P14.Z, P0.B // c0f11825
PRDFFRS P14.Z, P0.B // c0f15825
PREV P14.S, P13.S // cd41b405
PSEL P4.B, P2.B, P1, P14.B // 5e460425
PTRN1 P5.D, P4.D, P2.D // 8250e505
PTRN2 P5.D, P4.D, P2.D // 8254e505
PUZP1 P5.D, P4.D, P2.D // 8248e505
PUZP2 P5.D, P4.D, P2.D // 824ce505
PWRFFR P13.B // a0912825
PZIP1 P5.D, P4.D, P2.D // 8240e505
PZIP2 P5.D, P4.D, P2.D // 8244e505
SETFFR // 00902c25
ZABS Z7.D, P4.M, Z13.D // edb0d604
ZABS Z7.D, P4.Z, Z13.D // edb0c604
ZADCLB Z7.D, Z23.D, Z13.D // edd24745
ZADCLT Z7.D, Z23.D, Z13.D // edd64745
ZADD Z15.B, Z0.B, P3.M, Z0.B // e00d0004
ZADD Z7.D, Z23.D, Z13.D // ed02e704
ZADDHNB Z22.S, Z10.S, Z8.H // 4861b645
ZADDHNT Z22.S, Z10.S, Z8.H // 4865b645
ZADDP Z15.B, Z0.B, P3.M, Z0.B // e0ad1144
ZADDPT Z23.D, Z13.D, P1.M, Z13.D // ed06c404
ZADDPT Z7.D, Z6.D, Z23.D // d708e704
// TODO: ADDQP
ZADDQV Z25.S, P3, V5.S4 // 252f8504
// TODO: ADDSUBP
ZAESD Z7.B, Z6.B, Z6.B // e6e42245
ZAESE Z7.B, Z6.B, Z6.B // e6e02245
ZAESIMC Z11.B, Z11.B // 0be42045
ZAESMC Z11.B, Z11.B // 0be02045
ZAND Z15.B, Z0.B, P3.M, Z0.B // e00d1a04
ZAND Z7.D, Z6.D, Z23.D // d7302704
ZANDQV Z25.S, P3, V5.S4 // 252f9e04
ZASR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd004
ZASR Z15.B, Z0.B, P3.M, Z0.B // e08d1004
ZASR Z7.D, Z6.H, Z13.H // cd806704
ZASRR Z15.B, Z0.B, P3.M, Z0.B // e08d1404
ZBCAX Z23.D, Z13.D, Z21.D, Z21.D // f53a6d04
ZBDEP Z7.D, Z23.D, Z13.D // edb6c745
ZBEXT Z7.D, Z23.D, Z13.D // edb2c745
ZBF1CVT Z11.B, Z6.H // 66390865
ZBF1CVTLT Z11.B, Z6.H // 66390965
ZBF2CVT Z11.B, Z6.H // 663d0865
ZBF2CVTLT Z11.B, Z6.H // 663d0965
ZBFADD Z23.H, Z13.H, P1.M, Z13.H // ed860065
ZBFADD Z7.H, Z6.H, Z23.H // d7000765
ZBFCLAMP Z7.H, Z6.H, Z23.H // d7242764
ZBFCVT Z13.S, P1.Z, Z22.H // b6c59a64
ZBFCVT Z13.S, P1.M, Z22.H // b6a58a65
ZBFCVTNT Z13.S, P1.M, Z22.H // b6a58a64
ZBFCVTNT Z13.S, P1.Z, Z22.H // b6a58264
ZBFDOT Z7.H, Z6.H, Z23.S // d7806764
ZBFMAX Z23.H, Z13.H, P1.M, Z13.H // ed860665
ZBFMAXNM Z23.H, Z13.H, P1.M, Z13.H // ed860465
ZBFMIN Z23.H, Z13.H, P1.M, Z13.H // ed860765
ZBFMINNM Z23.H, Z13.H, P1.M, Z13.H // ed860565
ZBFMLA Z23.H, Z13.H, P1.M, Z22.H // b6053765
ZBFMLALB Z7.H, Z6.H, Z23.S // d780e764
ZBFMLALT Z7.H, Z6.H, Z23.S // d784e764
ZBFMLS Z23.H, Z13.H, P1.M, Z22.H // b6253765
ZBFMLSLB Z7.H, Z6.H, Z23.S // d7a0e764
ZBFMLSLT Z7.H, Z6.H, Z23.S // d7a4e764
// TODO: BFMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZBFMMLA Z7.H, Z6.H, Z23.S // d7e46764
ZBFMUL Z23.H, Z13.H, P1.M, Z13.H // ed860265
ZBFMUL Z7.H, Z6.H, Z23.H // d7080765
ZBFSCALE Z23.H, Z13.H, P1.M, Z13.H // ed860965
ZBFSUB Z7.H, Z6.H, Z23.H // d7040765
ZBFSUB Z23.H, Z13.H, P1.M, Z13.H // ed860165
ZBGRP Z7.D, Z23.D, Z13.D // edbac745
ZBIC Z15.B, Z0.B, P3.M, Z0.B // e00d1b04
ZBIC Z7.D, Z6.D, Z23.D // d730e704
ZBSL Z23.D, Z13.D, Z21.D, Z21.D // f53e2d04
ZBSL1N Z23.D, Z13.D, Z21.D, Z21.D // f53e6d04
ZBSL2N Z23.D, Z13.D, Z21.D, Z21.D // f53ead04
ZCLASTA Z15.B, Z0.B, P3, Z0.B // e08d2805
ZCLASTB Z15.B, Z0.B, P3, Z0.B // e08d2905
ZCLS Z7.D, P4.Z, Z13.D // edb0c804
ZCLS Z7.D, P4.M, Z13.D // edb0d804
ZCLZ Z7.D, P4.Z, Z13.D // edb0c904
ZCLZ Z7.D, P4.M, Z13.D // edb0d904
ZCMPEQ Z0.H, Z2.H, P0.Z, P14.H // 4ea04024
ZCMPEQ Z0.D, Z12.S, P0.Z, P14.S // 8e218024
ZCMPGE Z0.H, Z2.H, P0.Z, P14.H // 4e804024
ZCMPGE Z0.D, Z12.S, P0.Z, P14.S // 8e418024
ZCMPGT Z0.H, Z2.H, P0.Z, P14.H // 5e804024
ZCMPGT Z0.D, Z12.S, P0.Z, P14.S // 9e418024
ZCMPHI Z0.D, Z12.S, P0.Z, P14.S // 9ec18024
ZCMPHI Z0.H, Z2.H, P0.Z, P14.H // 5e004024
ZCMPHS Z0.H, Z2.H, P0.Z, P14.H // 4e004024
ZCMPHS Z0.D, Z12.S, P0.Z, P14.S // 8ec18024
// TODO: CMPLE
// TODO: CMPLO
// TODO: CMPLS
// TODO: CMPLT
ZCMPNE Z0.D, Z12.S, P0.Z, P14.S // 9e218024
ZCMPNE Z0.H, Z2.H, P0.Z, P14.H // 5ea04024
ZCNOT Z7.D, P4.M, Z13.D // edb0db04
ZCNOT Z7.D, P4.Z, Z13.D // edb0cb04
ZCNT Z7.D, P4.M, Z13.D // edb0da04
ZCNT Z7.D, P4.Z, Z13.D // edb0ca04
ZCOMPACT Z7.D, P4, Z13.D // ed90e105
ZCOMPACT Z7.D, P4, Z13.D // ed90e105
ZDECP P14.S, Z26.S // da81ad25
ZEOR Z15.B, Z0.B, P3.M, Z0.B // e00d1904
ZEOR Z7.D, Z6.D, Z23.D // d730a704
ZEOR3 Z23.D, Z13.D, Z21.D, Z21.D // f53a2d04
ZEORBT Z7.D, Z23.D, Z13.D // ed92c745
ZEORQV Z25.S, P3, V5.S4 // 252f9d04
ZEORTB Z7.D, Z23.D, Z13.D // ed96c745
ZEXPAND Z7.D, P4, Z13.D // ed90f105
ZF1CVT Z11.B, Z6.H // 66310865
ZF1CVTLT Z11.B, Z6.H // 66310965
ZF2CVT Z11.B, Z6.H // 66350865
ZF2CVTLT Z11.B, Z6.H // 66350965
ZFABD Z25.S, Z2.S, P1.M, Z2.S // 22878865
ZFABS Z7.D, P4.Z, Z13.D // edb0cc04
ZFABS Z7.D, P4.M, Z13.D // edb0dc04
ZFACGE Z0.H, Z2.H, P0.Z, P14.H // 5ec04065
ZFACGT Z0.H, Z2.H, P0.Z, P14.H // 5ee04065
ZFADD Z25.S, Z2.S, P1.M, Z2.S // 22878065
ZFADD Z7.D, Z23.D, Z13.D // ed02c765
ZFADDP Z25.S, Z2.S, P1.M, Z2.S // 22879064
ZFADDQV Z25.S, P3, V5.S4 // 25af9064
ZFAMAX Z25.S, Z2.S, P1.M, Z2.S // 22878e65
ZFAMIN Z25.S, Z2.S, P1.M, Z2.S // 22878f65
ZFCLAMP Z7.D, Z23.D, Z13.D // ed26e764
ZFCMEQ Z0.H, Z2.H, P0.Z, P14.H // 4e604065
ZFCMGE Z0.H, Z2.H, P0.Z, P14.H // 4e404065
ZFCMGT Z0.H, Z2.H, P0.Z, P14.H // 5e404065
ZFCMNE Z0.H, Z2.H, P0.Z, P14.H // 5e604065
ZFCMUO Z0.H, Z2.H, P0.Z, P14.H // 4ec04065
ZFCVT Z13.H, P1.M, Z22.S // b6a58965
ZFCVT Z13.S, P1.M, Z22.D // b6a5cb65
ZFCVT Z13.H, P1.Z, Z22.S // b6a59a64
ZFCVT Z13.H, P1.M, Z22.D // b6a5c965
ZFCVT Z13.H, P1.Z, Z22.D // b6a5da64
ZFCVT Z13.S, P1.M, Z22.H // b6a58865
ZFCVT Z13.S, P1.Z, Z22.H // b6859a64
ZFCVT Z13.S, P1.Z, Z22.D // b6e5da64
ZFCVT Z13.D, P1.M, Z22.H // b6a5c865
ZFCVT Z13.D, P1.Z, Z22.H // b685da64
ZFCVT Z13.D, P1.M, Z22.S // b6a5ca65
ZFCVT Z13.D, P1.Z, Z22.S // b6c5da64
ZFCVTLT Z13.H, P1.M, Z22.S // b6a58964
ZFCVTLT Z13.H, P1.Z, Z22.S // b6a58164
ZFCVTLT Z13.S, P1.M, Z22.D // b6a5cb64
ZFCVTLT Z13.S, P1.Z, Z22.D // b6a5c364
ZFCVTNT Z13.S, P1.M, Z22.H // b6a58864
ZFCVTNT Z13.S, P1.Z, Z22.H // b6a58064
ZFCVTNT Z13.D, P1.M, Z22.S // b6a5ca64
ZFCVTNT Z13.D, P1.Z, Z22.S // b6a5c264
ZFCVTX Z13.D, P1.Z, Z22.S // b6c51a64
ZFCVTX Z13.D, P1.M, Z22.S // b6a50a65
ZFCVTXNT Z13.D, P1.M, Z22.S // b6a50a64
ZFCVTXNT Z13.D, P1.Z, Z22.S // b6a50264
ZFCVTZS Z13.H, P1.M, Z22.H // b6a55a65
ZFCVTZS Z13.H, P1.Z, Z22.H // b6c55e64
ZFCVTZS Z13.H, P1.M, Z22.S // b6a55c65
ZFCVTZS Z13.H, P1.Z, Z22.S // b6855f64
ZFCVTZS Z13.H, P1.M, Z22.D // b6a55e65
ZFCVTZS Z13.H, P1.Z, Z22.D // b6c55f64
ZFCVTZS Z13.S, P1.M, Z22.S // b6a59c65
ZFCVTZS Z13.S, P1.Z, Z22.S // b6859f64
ZFCVTZS Z13.S, P1.M, Z22.D // b6a5dc65
ZFCVTZS Z13.S, P1.Z, Z22.D // b685df64
ZFCVTZS Z13.D, P1.M, Z22.S // b6a5d865
ZFCVTZS Z13.D, P1.Z, Z22.S // b685de64
ZFCVTZS Z13.D, P1.M, Z22.D // b6a5de65
ZFCVTZS Z13.D, P1.Z, Z22.D // b6c5df64
ZFCVTZU Z13.D, P1.Z, Z22.S // b6a5de64
ZFCVTZU Z13.H, P1.M, Z22.D // b6a55f65
ZFCVTZU Z13.H, P1.M, Z22.H // b6a55b65
ZFCVTZU Z13.H, P1.Z, Z22.H // b6e55e64
ZFCVTZU Z13.D, P1.Z, Z22.D // b6e5df64
ZFCVTZU Z13.H, P1.M, Z22.S // b6a55d65
ZFCVTZU Z13.H, P1.Z, Z22.S // b6a55f64
ZFCVTZU Z13.H, P1.Z, Z22.D // b6e55f64
ZFCVTZU Z13.D, P1.M, Z22.D // b6a5df65
ZFCVTZU Z13.S, P1.M, Z22.S // b6a59d65
ZFCVTZU Z13.D, P1.M, Z22.S // b6a5d965
ZFCVTZU Z13.S, P1.Z, Z22.D // b6a5df64
ZFCVTZU Z13.S, P1.M, Z22.D // b6a5dd65
ZFCVTZU Z13.S, P1.Z, Z22.S // b6a59f64
ZFDIV Z25.S, Z2.S, P1.M, Z2.S // 22878d65
ZFDIVR Z25.S, Z2.S, P1.M, Z2.S // 22878c65
ZFDOT Z7.B, Z6.B, Z23.S // d7846764
ZFDOT Z7.B, Z6.B, Z23.H // d7842764
ZFDOT Z7.H, Z6.H, Z23.S // d7802764
ZFEXPA Z1.S, Z26.S // 3ab8a004
ZFLOGB Z7.D, P4.M, Z13.D // edb01e65
ZFLOGB Z7.D, P4.Z, Z13.D // edf01e64
ZFMAD Z0.H, Z2.H, P0.M, Z14.H // 4e806065
ZFMAX Z25.S, Z2.S, P1.M, Z2.S // 22878665
ZFMAXNM Z25.S, Z2.S, P1.M, Z2.S // 22878465
ZFMAXNMP Z25.S, Z2.S, P1.M, Z2.S // 22879464
ZFMAXNMQV Z25.S, P3, V5.S4 // 25af9464
ZFMAXP Z25.S, Z2.S, P1.M, Z2.S // 22879664
ZFMAXQV Z25.S, P3, V5.S4 // 25af9664
ZFMIN Z25.S, Z2.S, P1.M, Z2.S // 22878765
ZFMINNM Z25.S, Z2.S, P1.M, Z2.S // 22878565
ZFMINNMP Z25.S, Z2.S, P1.M, Z2.S // 22879564
ZFMINNMQV Z25.S, P3, V5.S4 // 25af9564
ZFMINP Z25.S, Z2.S, P1.M, Z2.S // 22879764
ZFMINQV Z25.S, P3, V5.S4 // 25af9764
ZFMLA Z0.H, Z2.H, P0.M, Z14.H // 4e006065
ZFMLALB Z7.H, Z6.H, Z23.S // d780a764
ZFMLALB Z7.B, Z6.B, Z23.H // d788a764
ZFMLALLBB Z7.B, Z6.B, Z23.S // d7882764
ZFMLALLBT Z7.B, Z6.B, Z23.S // d7982764
ZFMLALLTB Z7.B, Z6.B, Z23.S // d7a82764
ZFMLALLTT Z7.B, Z6.B, Z23.S // d7b82764
ZFMLALT Z7.B, Z6.B, Z23.H // d798a764
ZFMLALT Z7.H, Z6.H, Z23.S // d784a764
ZFMLS Z0.H, Z2.H, P0.M, Z14.H // 4e206065
ZFMLSLB Z7.H, Z6.H, Z23.S // d7a0a764
ZFMLSLT Z7.H, Z6.H, Z23.S // d7a4a764
// TODO: FMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZFMMLA Z7.S, Z6.S, Z23.S // d7e4a764
ZFMMLA Z7.D, Z6.D, Z23.D // d7e4e764
ZFMMLA Z7.H, Z6.H, Z23.S // d7e42764
ZFMMLA Z7.B, Z6.B, Z23.H // d7e06764
ZFMMLA Z7.B, Z6.B, Z23.S // d7e02764
ZFMSB Z0.H, Z2.H, P0.M, Z14.H // 4ea06065
ZFMUL Z7.D, Z23.D, Z13.D // ed0ac765
ZFMUL Z25.S, Z2.S, P1.M, Z2.S // 22878265
ZFMULX Z25.S, Z2.S, P1.M, Z2.S // 22878a65
ZFNEG Z7.D, P4.M, Z13.D // edb0dd04
ZFNEG Z7.D, P4.Z, Z13.D // edb0cd04
ZFNMAD Z0.H, Z2.H, P0.M, Z14.H // 4ec06065
ZFNMLA Z0.H, Z2.H, P0.M, Z14.H // 4e406065
ZFNMLS Z0.H, Z2.H, P0.M, Z14.H // 4e606065
ZFNMSB Z0.H, Z2.H, P0.M, Z14.H // 4ee06065
ZFRECPE Z1.S, Z26.S // 3a308e65
ZFRECPS Z7.D, Z23.D, Z13.D // ed1ac765
ZFRECPX Z7.D, P4.M, Z13.D // edb0cc65
ZFRECPX Z7.D, P4.Z, Z13.D // ed90db64
ZFRINT32X Z7.D, P4.M, Z13.D // edb01365
ZFRINT32X Z7.D, P4.Z, Z13.D // edf01c64
ZFRINT32Z Z7.D, P4.Z, Z13.D // edd01c64
ZFRINT32Z Z7.D, P4.M, Z13.D // edb01265
ZFRINT64X Z7.D, P4.Z, Z13.D // edf01d64
ZFRINT64X Z7.D, P4.M, Z13.D // edb01765
ZFRINT64Z Z7.D, P4.M, Z13.D // edb01665
ZFRINT64Z Z7.D, P4.Z, Z13.D // edd01d64
ZFRINTA Z7.D, P4.M, Z13.D // edb0c465
ZFRINTA Z7.D, P4.Z, Z13.D // ed90d964
ZFRINTI Z7.D, P4.Z, Z13.D // edf0d964
ZFRINTI Z7.D, P4.M, Z13.D // edb0c765
ZFRINTM Z7.D, P4.Z, Z13.D // edd0d864
ZFRINTM Z7.D, P4.M, Z13.D // edb0c265
ZFRINTN Z7.D, P4.M, Z13.D // edb0c065
ZFRINTN Z7.D, P4.Z, Z13.D // ed90d864
ZFRINTP Z7.D, P4.M, Z13.D // edb0c165
ZFRINTP Z7.D, P4.Z, Z13.D // edb0d864
ZFRINTX Z7.D, P4.Z, Z13.D // edd0d964
ZFRINTX Z7.D, P4.M, Z13.D // edb0c665
ZFRINTZ Z7.D, P4.M, Z13.D // edb0c365
ZFRINTZ Z7.D, P4.Z, Z13.D // edf0d864
ZFRSQRTE Z1.S, Z26.S // 3a308f65
ZFRSQRTS Z7.D, Z23.D, Z13.D // ed1ec765
ZFSCALE Z25.S, Z2.S, P1.M, Z2.S // 22878965
ZFSQRT Z7.D, P4.Z, Z13.D // edb0db64
ZFSQRT Z7.D, P4.M, Z13.D // edb0cd65
ZFSUB Z7.D, Z23.D, Z13.D // ed06c765
ZFSUB Z25.S, Z2.S, P1.M, Z2.S // 22878165
ZFSUBR Z25.S, Z2.S, P1.M, Z2.S // 22878365
ZFTSMUL Z7.D, Z23.D, Z13.D // ed0ec765
ZFTSSEL Z7.D, Z23.D, Z13.D // edb2e704
ZHISTCNT Z19.S, Z20.S, P1.Z, Z2.S // 82c6b345
ZHISTSEG Z7.B, Z6.B, Z23.B // d7a02745
ZINCP P14.S, Z26.S // da81ac25
ZLSL Z15.B, Z0.B, P3.M, Z0.B // e08d1304
ZLSL Z2.D, Z10.D, P3.M, Z10.D // 4a8cd304
ZLSL Z7.D, Z6.H, Z13.H // cd8c6704
ZLSLR Z15.B, Z0.B, P3.M, Z0.B // e08d1704
ZLSR Z15.B, Z0.B, P3.M, Z0.B // e08d1104
ZLSR Z7.D, Z6.H, Z13.H // cd846704
ZLSR Z2.D, Z10.D, P3.M, Z10.D // 4a8cd104
ZLSRR Z15.B, Z0.B, P3.M, Z0.B // e08d1504
ZMAD Z0.H, Z2.H, P0.M, Z14.H // 0ec04204
ZMADPT Z7.D, Z6.D, Z23.D // f7d8c644
ZMATCH Z0.H, Z2.H, P0.Z, P14.H // 4e806045
ZMLA Z0.H, Z2.H, P0.M, Z14.H // 4e404004
ZMLAPT Z7.D, Z6.D, Z23.D // d7d0c744
ZMLS Z0.H, Z2.H, P0.M, Z14.H // 4e604004
ZMOVPRFX Z7.D, P4.Z, Z21.D // f530d004
ZMOVPRFX Z11, Z6 // 66bd2004
ZMSB Z0.H, Z2.H, P0.M, Z14.H // 0ee04204
ZMUL Z7.D, Z23.D, Z13.D // ed62e704
ZMUL Z15.B, Z0.B, P3.M, Z0.B // e00d1004
ZNBSL Z23.D, Z13.D, Z21.D, Z21.D // f53eed04
ZNEG Z7.D, P4.M, Z13.D // edb0d704
ZNEG Z7.D, P4.Z, Z13.D // edb0c704
ZNMATCH Z0.H, Z2.H, P0.Z, P14.H // 5e806045
ZNOT Z7.D, P4.M, Z13.D // edb0de04
ZNOT Z7.D, P4.Z, Z13.D // edb0ce04
ZORQV Z25.S, P3, V5.S4 // 252f9c04
ZORR Z15.B, Z0.B, P3.M, Z0.B // e00d1804
ZORR Z7.D, Z6.D, Z23.D // d7306704
ZPMOV P14.B, Z6 // c6392b05
ZPMOV Z11, P0.B // 60392a05
ZPMUL Z7.B, Z6.B, Z23.B // d7642704
ZPMULLB Z8.B, Z4.B, Z30.H // 9e684845
ZPMULLB Z7.D, Z6.D, Z23.Q // d7680745
ZPMULLT Z7.D, Z6.D, Z23.Q // d76c0745
ZPMULLT Z8.B, Z4.B, Z30.H // 9e6c4845
ZRADDHNB Z22.S, Z10.S, Z8.H // 4869b645
ZRADDHNT Z22.S, Z10.S, Z8.H // 486db645
ZRAX1 Z7.D, Z6.D, Z23.D // d7f42745
ZRBIT Z7.D, P4.Z, Z13.D // edb0e705
ZRBIT Z7.D, P4.M, Z13.D // ed90e705
ZREV Z1.S, Z26.S // 3a38b805
ZREVB Z7.D, P4.Z, Z13.D // edb0e405
ZREVB Z7.D, P4.M, Z13.D // ed90e405
ZREVD Z13.Q, P1.M, Z22.Q // b6852e05
ZREVD Z13.Q, P1.Z, Z22.Q // b6a52e05
ZREVH Z7.D, P4.Z, Z13.D // edb0e505
ZREVH Z7.D, P4.M, Z13.D // ed90e505
ZREVW Z13.D, P1.Z, Z22.D // b6a5e605
ZREVW Z13.D, P1.M, Z22.D // b685e605
ZRSUBHNB Z22.S, Z10.S, Z8.H // 4879b645
ZRSUBHNT Z22.S, Z10.S, Z8.H // 487db645
ZSABA Z7.D, Z23.D, Z13.D // edfac745
// TODO: SABAL <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
ZSABALB Z8.B, Z4.B, Z30.H // 9ec04845
ZSABALT Z8.B, Z4.B, Z30.H // 9ec44845
ZSABD Z15.B, Z0.B, P3.M, Z0.B // e00d0c04
ZSABDLB Z8.B, Z4.B, Z30.H // 9e304845
ZSABDLT Z8.B, Z4.B, Z30.H // 9e344845
ZSADALP Z14.S, P1.M, Z1.D // c1a5c444
ZSADDLB Z8.B, Z4.B, Z30.H // 9e004845
ZSADDLBT Z8.B, Z4.B, Z30.H // 9e804845
ZSADDLT Z8.B, Z4.B, Z30.H // 9e044845
ZSADDWB Z22.S, Z10.D, Z5.D // 4541d645
ZSADDWT Z22.S, Z10.D, Z5.D // 4545d645
ZSBCLB Z7.D, Z23.D, Z13.D // edd2c745
ZSBCLT Z7.D, Z23.D, Z13.D // edd6c745
ZSCLAMP Z7.D, Z23.D, Z13.D // edc2c744
ZSCVTF Z13.S, P1.M, Z22.D // b6a5d065
// TODO: SCVTF <Zd>.<T>, <Zn>.<Tb>
ZSCVTF Z13.D, P1.M, Z22.S // b6a5d465
ZSCVTF Z13.D, P1.Z, Z22.S // b685dd64
ZSCVTF Z13.D, P1.M, Z22.D // b6a5d665
ZSCVTF Z13.D, P1.Z, Z22.D // b6c5dd64
ZSCVTF Z13.H, P1.Z, Z22.H // b6c55c64
ZSCVTF Z13.S, P1.M, Z22.H // b6a55465
ZSCVTF Z13.S, P1.Z, Z22.H // b6855d64
ZSCVTF Z13.D, P1.Z, Z22.H // b6c55d64
ZSCVTF Z13.D, P1.M, Z22.H // b6a55665
ZSCVTF Z13.S, P1.Z, Z22.D // b685dc64
ZSCVTF Z13.H, P1.M, Z22.H // b6a55265
ZSCVTF Z13.S, P1.Z, Z22.S // b6859d64
ZSCVTF Z13.S, P1.M, Z22.S // b6a59465
// TODO: SCVTFLT
ZSDIV Z25.S, Z2.S, P1.M, Z2.S // 22079404
ZSDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079604
ZSDOT Z15.B, Z0.B, Z12.S // 0c008f44
ZSDOT Z7.H, Z6.H, Z23.S // d7c80744
// TODO: SDOT <Zda>.H, <Zn>.B, <Zm>.B
ZSEL Z23.B, Z21.B, P14, Z2.B // a2fa3705
ZSHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1044
ZSHSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1244
ZSHSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1644
ZSM4E Z7.S, Z6.S, Z6.S // e6e02345
ZSM4EKEY Z7.S, Z6.S, Z23.S // d7f02745
ZSMAX Z15.B, Z0.B, P3.M, Z0.B // e00d0804
ZSMAXP Z15.B, Z0.B, P3.M, Z0.B // e0ad1444
ZSMAXQV Z25.S, P3, V5.S4 // 252f8c04
ZSMIN Z15.B, Z0.B, P3.M, Z0.B // e00d0a04
ZSMINP Z15.B, Z0.B, P3.M, Z0.B // e0ad1644
ZSMINQV Z25.S, P3, V5.S4 // 252f8e04
ZSMLALB Z8.B, Z4.B, Z30.H // 9e404844
ZSMLALT Z8.B, Z4.B, Z30.H // 9e444844
ZSMLSLB Z8.B, Z4.B, Z30.H // 9e504844
ZSMLSLT Z8.B, Z4.B, Z30.H // 9e544844
ZSMMLA Z7.B, Z6.B, Z23.S // d7980745
ZSMULH Z7.D, Z23.D, Z13.D // ed6ae704
ZSMULH Z15.B, Z0.B, P3.M, Z0.B // e00d1204
ZSMULLB Z8.B, Z4.B, Z30.H // 9e704845
ZSMULLT Z8.B, Z4.B, Z30.H // 9e744845
ZSPLICE Z15.B, Z0.B, P3, Z0.B // e08d2c05
ZSQABS Z7.D, P4.M, Z13.D // edb0c844
ZSQABS Z7.D, P4.Z, Z13.D // edb0ca44
ZSQADD Z7.D, Z23.D, Z13.D // ed12e704
ZSQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1844
ZSQDECP P14.S, Z26.S // da81aa25
ZSQDMLALB Z8.B, Z4.B, Z30.H // 9e604844
ZSQDMLALBT Z8.B, Z4.B, Z30.H // 9e084844
ZSQDMLALT Z8.B, Z4.B, Z30.H // 9e644844
ZSQDMLSLB Z8.B, Z4.B, Z30.H // 9e684844
ZSQDMLSLBT Z8.B, Z4.B, Z30.H // 9e0c4844
ZSQDMLSLT Z8.B, Z4.B, Z30.H // 9e6c4844
ZSQDMULH Z7.D, Z23.D, Z13.D // ed72e704
ZSQDMULLB Z8.B, Z4.B, Z30.H // 9e604845
ZSQDMULLT Z8.B, Z4.B, Z30.H // 9e644845
ZSQINCP P14.S, Z26.S // da81a825
ZSQNEG Z7.D, P4.M, Z13.D // edb0c944
ZSQNEG Z7.D, P4.Z, Z13.D // edb0cb44
ZSQRDMLAH Z7.D, Z23.D, Z13.D // ed72c744
ZSQRDMLSH Z7.D, Z23.D, Z13.D // ed76c744
ZSQRDMULH Z7.D, Z23.D, Z13.D // ed76e704
ZSQRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0a44
ZSQRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0e44
ZSQSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0844
ZSQSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0c44
ZSQSUB Z7.D, Z23.D, Z13.D // ed1ae704
ZSQSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1a44
ZSQSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1e44
ZSQXTNB Z30.D, Z29.S // dd436045
ZSQXTNT Z30.D, Z29.S // dd476045
ZSQXTUNB Z30.D, Z29.S // dd536045
ZSQXTUNT Z30.D, Z29.S // dd576045
ZSRHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1444
ZSRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0244
ZSRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0644
ZSSUBLB Z8.B, Z4.B, Z30.H // 9e104845
ZSSUBLBT Z8.B, Z4.B, Z30.H // 9e884845
ZSSUBLT Z8.B, Z4.B, Z30.H // 9e144845
ZSSUBLTB Z8.B, Z4.B, Z30.H // 9e8c4845
ZSSUBWB Z22.S, Z10.D, Z5.D // 4551d645
ZSSUBWT Z22.S, Z10.D, Z5.D // 4555d645
ZSUB Z7.D, Z23.D, Z13.D // ed06e704
ZSUB Z15.B, Z0.B, P3.M, Z0.B // e00d0104
ZSUBHNB Z22.S, Z10.S, Z8.H // 4871b645
ZSUBHNT Z22.S, Z10.S, Z8.H // 4875b645
// TODO: SUBP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
ZSUBPT Z7.D, Z6.D, Z23.D // d70ce704
ZSUBPT Z23.D, Z13.D, P1.M, Z13.D // ed06c504
ZSUBR Z15.B, Z0.B, P3.M, Z0.B // e00d0304
ZSUNPKHI Z15.B, Z0.H // e0397105
ZSUNPKLO Z15.B, Z0.H // e0397005
ZSUQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1c44
ZSXTB Z7.D, P4.Z, Z13.D // edb0c004
ZSXTB Z7.D, P4.M, Z13.D // edb0d004
ZSXTH Z7.D, P4.M, Z13.D // edb0d204
ZSXTH Z7.D, P4.Z, Z13.D // edb0c204
ZSXTW Z13.D, P1.M, Z22.D // b6a5d404
ZSXTW Z13.D, P1.Z, Z22.D // b6a5c404
ZTBX Z7.D, Z23.D, Z13.D // ed2ee705
ZTBXQ Z7.D, Z23.D, Z13.D // ed36e705
ZTRN1 Z7.D, Z23.D, Z13.D // ed72e705
ZTRN1 Z7.Q, Z6.Q, Z23.Q // d718a705
ZTRN2 Z7.D, Z23.D, Z13.D // ed76e705
ZTRN2 Z7.Q, Z6.Q, Z23.Q // d71ca705
ZUABA Z7.D, Z23.D, Z13.D // edfec745
// TODO: UABAL <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
ZUABALB Z8.B, Z4.B, Z30.H // 9ec84845
ZUABALT Z8.B, Z4.B, Z30.H // 9ecc4845
ZUABD Z15.B, Z0.B, P3.M, Z0.B // e00d0d04
ZUABDLB Z8.B, Z4.B, Z30.H // 9e384845
ZUABDLT Z8.B, Z4.B, Z30.H // 9e3c4845
ZUADALP Z14.S, P1.M, Z1.D // c1a5c544
ZUADDLB Z8.B, Z4.B, Z30.H // 9e084845
ZUADDLT Z8.B, Z4.B, Z30.H // 9e0c4845
ZUADDWB Z22.S, Z10.D, Z5.D // 4549d645
ZUADDWT Z22.S, Z10.D, Z5.D // 454dd645
ZUCLAMP Z7.D, Z23.D, Z13.D // edc6c744
ZUCVTF Z13.D, P1.Z, Z22.S // b6a5dd64
ZUCVTF Z13.D, P1.M, Z22.H // b6a55765
ZUCVTF Z13.S, P1.Z, Z22.H // b6a55d64
ZUCVTF Z13.S, P1.M, Z22.S // b6a59565
ZUCVTF Z13.S, P1.Z, Z22.S // b6a59d64
ZUCVTF Z13.S, P1.M, Z22.D // b6a5d165
ZUCVTF Z13.S, P1.Z, Z22.D // b6a5dc64
ZUCVTF Z13.H, P1.M, Z22.H // b6a55365
ZUCVTF Z13.D, P1.Z, Z22.H // b6e55d64
ZUCVTF Z13.D, P1.M, Z22.S // b6a5d565
ZUCVTF Z13.H, P1.Z, Z22.H // b6e55c64
ZUCVTF Z13.D, P1.M, Z22.D // b6a5d765
ZUCVTF Z13.D, P1.Z, Z22.D // b6e5dd64
ZUCVTF Z13.S, P1.M, Z22.H // b6a55565
// TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
// TODO: UCVTFLT
ZUDIV Z25.S, Z2.S, P1.M, Z2.S // 22079504
ZUDIVR Z25.S, Z2.S, P1.M, Z2.S // 22079704
// TODO: UDOT <Zda>.H, <Zn>.B, <Zm>.B
ZUDOT Z7.H, Z6.H, Z23.S // d7cc0744
ZUDOT Z15.B, Z0.B, Z12.S // 0c048f44
ZUHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1144
ZUHSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1344
ZUHSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1744
ZUMAX Z15.B, Z0.B, P3.M, Z0.B // e00d0904
ZUMAXP Z15.B, Z0.B, P3.M, Z0.B // e0ad1544
ZUMAXQV Z25.S, P3, V5.S4 // 252f8d04
ZUMIN Z15.B, Z0.B, P3.M, Z0.B // e00d0b04
ZUMINP Z15.B, Z0.B, P3.M, Z0.B // e0ad1744
ZUMINQV Z25.S, P3, V5.S4 // 252f8f04
ZUMLALB Z8.B, Z4.B, Z30.H // 9e484844
ZUMLALT Z8.B, Z4.B, Z30.H // 9e4c4844
ZUMLSLB Z8.B, Z4.B, Z30.H // 9e584844
ZUMLSLT Z8.B, Z4.B, Z30.H // 9e5c4844
ZUMMLA Z7.B, Z6.B, Z23.S // d798c745
ZUMULH Z15.B, Z0.B, P3.M, Z0.B // e00d1304
ZUMULH Z7.D, Z23.D, Z13.D // ed6ee704
ZUMULLB Z8.B, Z4.B, Z30.H // 9e784845
ZUMULLT Z8.B, Z4.B, Z30.H // 9e7c4845
ZUQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1944
ZUQADD Z7.D, Z23.D, Z13.D // ed16e704
ZUQDECP P14.S, Z26.S // da81ab25
ZUQINCP P14.S, Z26.S // da81a925
ZUQRSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0b44
ZUQRSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0f44
ZUQSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0944
ZUQSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0d44
ZUQSUB Z15.B, Z0.B, P3.M, Z0.B // e08d1b44
ZUQSUB Z7.D, Z23.D, Z13.D // ed1ee704
ZUQSUBR Z15.B, Z0.B, P3.M, Z0.B // e08d1f44
ZUQXTNB Z30.D, Z29.S // dd4b6045
ZUQXTNT Z30.D, Z29.S // dd4f6045
ZURECPE Z13.S, P1.M, Z22.S // b6a58044
ZURECPE Z13.S, P1.Z, Z22.S // b6a58244
ZURHADD Z15.B, Z0.B, P3.M, Z0.B // e08d1544
ZURSHL Z15.B, Z0.B, P3.M, Z0.B // e08d0344
ZURSHLR Z15.B, Z0.B, P3.M, Z0.B // e08d0744
ZURSQRTE Z13.S, P1.M, Z22.S // b6a58144
ZURSQRTE Z13.S, P1.Z, Z22.S // b6a58344
ZUSDOT Z7.B, Z6.B, Z23.S // d7788744
ZUSMMLA Z7.B, Z6.B, Z23.S // d7988745
ZUSQADD Z15.B, Z0.B, P3.M, Z0.B // e08d1d44
ZUSUBLB Z8.B, Z4.B, Z30.H // 9e184845
ZUSUBLT Z8.B, Z4.B, Z30.H // 9e1c4845
ZUSUBWB Z22.S, Z10.D, Z5.D // 4559d645
ZUSUBWT Z22.S, Z10.D, Z5.D // 455dd645
ZUUNPKHI Z15.B, Z0.H // e0397305
ZUUNPKLO Z15.B, Z0.H // e0397205
ZUXTB Z7.D, P4.M, Z13.D // edb0d104
ZUXTB Z7.D, P4.Z, Z13.D // edb0c104
ZUXTH Z7.D, P4.M, Z13.D // edb0d304
ZUXTH Z7.D, P4.Z, Z13.D // edb0c304
ZUXTW Z13.D, P1.M, Z22.D // b6a5d504
ZUXTW Z13.D, P1.Z, Z22.D // b6a5c504
ZUZP1 Z7.D, Z23.D, Z13.D // ed6ae705
ZUZP1 Z7.Q, Z6.Q, Z23.Q // d708a705
ZUZP2 Z7.D, Z23.D, Z13.D // ed6ee705
ZUZP2 Z7.Q, Z6.Q, Z23.Q // d70ca705
ZUZPQ1 Z7.D, Z23.D, Z13.D // edeac744
ZUZPQ2 Z7.D, Z23.D, Z13.D // edeec744
ZZIP1 Z7.D, Z23.D, Z13.D // ed62e705
ZZIP1 Z7.Q, Z6.Q, Z23.Q // d700a705
ZZIP2 Z7.D, Z23.D, Z13.D // ed66e705
ZZIP2 Z7.Q, Z6.Q, Z23.Q // d704a705
ZZIPQ1 Z7.D, Z23.D, Z13.D // ede2c744
ZZIPQ2 Z7.D, Z23.D, Z13.D // ede6c744
RET

581
src/cmd/asm/internal/asm/testdata/arm64sveerror.s vendored Normal file
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@@ -0,0 +1,581 @@
// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
#include "../../../../../runtime/textflag.h"
TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
PAND P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PANDS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBIC P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBICS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKA P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PBRKAS P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PBRKB P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PBRKBS P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PBRKN P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKNS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKPA P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKPAS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKPB P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PBRKPBS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PEOR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PEORS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PNAND P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PNANDS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PNOR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PNORS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PORN P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PORNS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PORR P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PORRS P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PPFALSE P14.S // ERROR "illegal combination from SVE"
PPFIRST P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PPNEXT P14.S, P13.Z, P14.B // ERROR "illegal combination from SVE"
PPTEST P14.S, P13.Z // ERROR "illegal combination from SVE"
PPTRUE PN5.D // ERROR "illegal combination from SVE"
PPUNPKHI P14.S, P13.S // ERROR "illegal combination from SVE"
PPUNPKLO P14.S, P13.S // ERROR "illegal combination from SVE"
PRDFFR P14.S // ERROR "illegal combination from SVE"
PRDFFR P14.Z, P13.S // ERROR "illegal combination from SVE"
PRDFFRS P14.Z, P13.S // ERROR "illegal combination from SVE"
PREV P14.B, P5.D // ERROR "illegal combination from SVE"
PSEL P14.S, P13.S, P14.M, P5.D // ERROR "illegal combination from SVE"
PTRN1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
PTRN2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
PUZP1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
PUZP2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
PWRFFR P14.S // ERROR "illegal combination from SVE"
PZIP1 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
PZIP2 P14.S, P13.S, P14.B // ERROR "illegal combination from SVE"
ZABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZADCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZADDHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZADDPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZADDPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
// TODO: ADDQP
ZADDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
// TODO: ADDSUBP
ZAESD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZAESE Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZAESIMC Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZAESMC Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZAND Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZAND Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZANDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZASR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZASR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZASRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBCAX Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZBDEP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBEXT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBF1CVT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBF1CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBF2CVT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBF2CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZBFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZBFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZBFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZBFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZBFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMAXNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMINNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: BFMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZBFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFSCALE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBFSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBGRP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBIC Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZBIC Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZBSL Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZBSL1N Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZBSL2N Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZCLASTA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZCLASTB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZCLS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCLS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCLZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCLZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCMPEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPHI Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPHI Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPHS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPHS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPLE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPLO Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPLS Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPLT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCMPNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZCNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZCOMPACT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZDECP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZEOR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEOR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZEOR3 Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZEORBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZEORTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZEXPAND Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZF1CVT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZF1CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZF2CVT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZF2CVTLT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZFABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFACGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFACGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFADDP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFADDQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZFAMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFAMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFCMEQ Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFCMGE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFCMGT Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFCMNE Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFCMUO Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTLT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTXNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTXNT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFCVTZU Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFEXPA Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZFLOGB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFLOGB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMAXNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMAXNMP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMAXNMQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZFMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZFMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMINNM Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMINNMP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMINNMQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZFMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZFMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALLBB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALLTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALLTT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: FMMLA <Zda>.H, <Zn>.H, <Zm>.H
ZFMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFMULX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFNMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFNMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFNMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFNMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFRECPE Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZFRECPS Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFRECPX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRECPX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT32X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT32X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT32Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT32Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT64X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT64X Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT64Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINT64Z Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTA Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTA Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTI Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTI Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTM Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTM Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTN Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTN Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRINTZ Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFRSQRTE Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZFRSQRTS Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFSCALE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFSQRT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFSQRT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZFSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZFTSMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZFTSSEL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZHISTCNT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZHISTSEG Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZINCP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZLSL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZLSRR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMAD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMADPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZMATCH Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZMLA Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMLAPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZMLS Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMOVPRFX Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZMOVPRFX Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZMSB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZMUL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZNBSL Z1.S, Z26.S, Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZNMATCH Z1.S, Z26.S, P14.M, P5.D // ERROR "illegal combination from SVE"
ZNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZNOT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZORQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZORR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZORR Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMOV P14.S, Z26.S // ERROR "illegal combination from SVE"
ZPMOV Z1.S, P13.S // ERROR "illegal combination from SVE"
ZPMUL Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZPMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZRADDHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZRADDHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZRAX1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZRBIT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZRBIT Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREV Z11.B, Z7.D // ERROR "illegal combination from SVE"
ZREVB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVD Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVD Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZREVW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZRSUBHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZRSUBHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSABA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: SABAL <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
ZSABALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSABALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSABDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSABDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSADALP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSADDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSADDLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSADDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSADDWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSADDWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSBCLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSBCLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
// TODO: SCVTF <Zd>.<T>, <Zn>.<Tb>
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
// TODO: SCVTFLT
ZSDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: SDOT <Zda>.H, <Zn>.B, <Zm>.B
ZSEL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSHSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSHSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSM4E Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSM4EKEY Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZSMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZSMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULH Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSPLICE Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSQABS Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQDECP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZSQDMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLALBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLSLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQDMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQINCP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZSQNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSQNEG Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSQRDMLAH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQRDMLSH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQRDMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSQSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSQXTNB Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSQXTNT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSQXTUNB Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSQXTUNT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSRHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSSUBLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBLBT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBLTB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSSUBWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSUBHNB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBHNT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: SUBP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
ZSUBPT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZSUBPT Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSUNPKHI Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSUNPKLO Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZSUQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZSXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZSXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZTBX Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZTBXQ Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZTRN1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZTRN1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZTRN2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZTRN2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUABA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
// TODO: UABAL <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
ZUABALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUABALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUABD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUABDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUABDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUADALP Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUADDLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUADDLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUADDWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUADDWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUCLAMP Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUCVTF Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
// TODO: UCVTF <Zd>.<T>, <Zn>.<Tb>
// TODO: UCVTFLT
ZUDIV Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUDIVR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
// TODO: UDOT <Zda>.H, <Zn>.B, <Zm>.B
ZUDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUHSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUHSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMAX Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMAXP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMAXQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZUMIN Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMINP Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMINQV Z1.S, P13.Z, V11.D2 // ERROR "illegal combination from SVE"
ZUMLALB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMLALT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMLSLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMLSLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMULH Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUMULH Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMULLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUMULLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQADD Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUQDECP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZUQINCP P14.B, Z7.D // ERROR "illegal combination from SVE"
ZUQRSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQRSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQSUB Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQSUB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUQSUBR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUQXTNB Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZUQXTNT Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZURECPE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZURECPE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZURHADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZURSHL Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZURSHLR Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZURSQRTE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZURSQRTE Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUSDOT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUSMMLA Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUSQADD Z1.S, Z26.S, P14.M, Z7.D // ERROR "illegal combination from SVE"
ZUSUBLB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUSUBLT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUSUBWB Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUSUBWT Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUUNPKHI Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZUUNPKLO Z1.S, Z26.S // ERROR "illegal combination from SVE"
ZUXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUXTB Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUXTH Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUXTW Z1.S, P13.Z, Z11.B // ERROR "illegal combination from SVE"
ZUZP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUZP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUZP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUZP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUZPQ1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZUZPQ2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIP1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIP2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIPQ1 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
ZZIPQ2 Z1.S, Z26.S, Z11.B // ERROR "illegal combination from SVE"
RET

176
src/cmd/internal/obj/arm64/a.out.go
View File

@@ -143,7 +143,77 @@ const (
REG_V30
REG_V31
REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
// SVE (Scalable Vector Extension) scalable vector registers
// The order matters, make sure that each
// kind of register starts numbering from the lowest bit.
REG_Z0
REG_Z1
REG_Z2
REG_Z3
REG_Z4
REG_Z5
REG_Z6
REG_Z7
REG_Z8
REG_Z9
REG_Z10
REG_Z11
REG_Z12
REG_Z13
REG_Z14
REG_Z15
REG_Z16
REG_Z17
REG_Z18
REG_Z19
REG_Z20
REG_Z21
REG_Z22
REG_Z23
REG_Z24
REG_Z25
REG_Z26
REG_Z27
REG_Z28
REG_Z29
REG_Z30
REG_Z31
REG_P0
REG_P1
REG_P2
REG_P3
REG_P4
REG_P5
REG_P6
REG_P7
REG_P8
REG_P9
REG_P10
REG_P11
REG_P12
REG_P13
REG_P14
REG_P15
REG_PN0
REG_PN1
REG_PN2
REG_PN3
REG_PN4
REG_PN5
REG_PN6
REG_PN7
REG_PN8
REG_PN9
REG_PN10
REG_PN11
REG_PN12
REG_PN13
REG_PN14
REG_PN15
REG_RSP = (REG_PN15 + 1) | 0x1f // to differentiate ZR/SP, REG_RSP&0x1f = 31
)
// bits 0-4 indicates register: Vn
@@ -152,15 +222,18 @@ const (
REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
REG_ELEM // Vn.<T>[index]
REG_ELEM_END
REG_ZARNG // Zn.<T>
REG_PARNGZM // Pn.<T> or Pn/M, Pn/Z
REG_PARNGZM_END
)
// Not registers, but flags that can be combined with regular register
// constants to indicate extended register conversion. When checking,
// you should subtract obj.RBaseARM64 first. From this difference, bit 11
// you should subtract obj.RBaseARM64 first. From this difference, bit 12
// indicates extended register, bits 8-10 select the conversion mode.
// REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
const REG_LSL = obj.RBaseARM64 + 1<<9
const REG_EXT = obj.RBaseARM64 + 1<<11
const REG_EXT = obj.RBaseARM64 + 1<<12
const (
REG_UXTB = REG_EXT + iota<<8
@@ -173,14 +246,14 @@ const (
REG_SXTX
)
// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
// Special registers, after subtracting obj.RBaseARM64, bit 13 indicates
// a special register and the low bits select the register.
// SYSREG_END is the last item in the automatically generated system register
// declaration, and it is defined in the sysRegEnc.go file.
// Define the special register after REG_SPECIAL, the first value of it should be
// REG_{name} = SYSREG_END + iota.
const (
REG_SPECIAL = obj.RBaseARM64 + 1<<12
REG_SPECIAL = obj.RBaseARM64 + 1<<13
)
// Register assignments:
@@ -250,6 +323,24 @@ var ARM64DWARFRegisters = map[int16]int16{
REG_R29: 29,
REG_R30: 30,
// SVE predicate registers
REG_P0: 48,
REG_P1: 49,
REG_P2: 50,
REG_P3: 51,
REG_P4: 52,
REG_P5: 53,
REG_P6: 54,
REG_P7: 55,
REG_P8: 56,
REG_P9: 57,
REG_P10: 58,
REG_P11: 59,
REG_P12: 60,
REG_P13: 61,
REG_P14: 62,
REG_P15: 63,
// floating point
REG_F0: 64,
REG_F1: 65,
@@ -317,6 +408,40 @@ var ARM64DWARFRegisters = map[int16]int16{
REG_V29: 93,
REG_V30: 94,
REG_V31: 95,
// SVE vector registers
REG_Z0: 96,
REG_Z1: 97,
REG_Z2: 98,
REG_Z3: 99,
REG_Z4: 100,
REG_Z5: 101,
REG_Z6: 102,
REG_Z7: 103,
REG_Z8: 104,
REG_Z9: 105,
REG_Z10: 106,
REG_Z11: 107,
REG_Z12: 108,
REG_Z13: 109,
REG_Z14: 110,
REG_Z15: 111,
REG_Z16: 112,
REG_Z17: 113,
REG_Z18: 114,
REG_Z19: 115,
REG_Z20: 116,
REG_Z21: 117,
REG_Z22: 118,
REG_Z23: 119,
REG_Z24: 120,
REG_Z25: 121,
REG_Z26: 122,
REG_Z27: 123,
REG_Z28: 124,
REG_Z29: 125,
REG_Z30: 126,
REG_Z31: 127,
}
const (
@@ -485,6 +610,42 @@ const (
C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
)
type AClass uint16 // operand type
// [insts] is sorted based on the order of these constants and the first match is chosen.
const (
AC_NONE AClass = iota
AC_REG // general purpose registers R0..R30 and ZR
AC_RSP // general purpose registers R0..R30 and RSP
AC_VREG // vector registers, such as V1
AC_ZREG // the scalable vector registers, such as Z1
AC_PREG // the scalable predicate registers, such as P1
AC_PREGZM // Pg.Z or Pg.M
AC_REGIDX // P8[1]
AC_ZREGIDX // Z1[1]
AC_PREGIDX // P0[R1, 1]
AC_ARNG // vector register with arrangement, such as Z1.D
AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1]
AC_IMM // constants
AC_REGLIST1 // list of 1 vector register, such as [Z1]
AC_REGLIST2 // list of 2 vector registers, such as [Z0, Z8]
AC_REGLIST3 // list of 3 vector registers, such as [Z1, Z2, Z3]
AC_REGLIST4 // list of 4 vector registers, such as [Z0, Z4, Z8, Z12]
AC_REGLIST_RANGE // list of vector register lists in range format, such as [Z0-Z4].
AC_MEMOFF // address with optional constant offset, the offset is an immediate, such as 4(Z1.D)
AC_MEMOFFMULVL // address with optional constant offset, the offset is an immediate multiplied by the vector's in-memory size, such as (2*VL)(Z1.D)
AC_MEMEXT // address with register offset with extensions, such as (Z2.D.UXTW<<3)(RSP)
AC_PREG_PATTERN // register with pattern, such as VL1*3(P1.D)
AC_REG_PATTERN // register with pattern, such as VL1*3(R1)
AC_ZREG_PATTERN // register with pattern, such as VL1*3(Z1.D)
AC_SPECIAL // VL*i pattern, one of: VL*2, VL*4, or prefetch pattern, such as PLDL1KEEP, more patterns might come in the future.
)
//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
const (
@@ -1027,7 +1188,7 @@ const (
AAUTIBSP
AAUTIA1716
AAUTIB1716
ALAST
ASVESTART
AB = obj.AJMP
ABL = obj.ACALL
)
@@ -1056,6 +1217,9 @@ const (
ARNG_H
ARNG_S
ARNG_D
ARNG_Q
PRED_M
PRED_Z
)
//go:generate stringer -type SpecialOperand -trimprefix SPOP_

1
src/cmd/internal/obj/arm64/anames.go
View File

@@ -544,5 +544,4 @@ var Anames = []string{
"AUTIBSP",
"AUTIA1716",
"AUTIB1716",
"LAST",
}

416
src/cmd/internal/obj/arm64/anames_gen.go Normal file
View File

@@ -0,0 +1,416 @@
// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
package arm64
var sveAnames = []string{
"SVESTART",
"PAND",
"PANDS",
"PBIC",
"PBICS",
"PBRKA",
"PBRKAS",
"PBRKB",
"PBRKBS",
"PBRKN",
"PBRKNS",
"PBRKPA",
"PBRKPAS",
"PBRKPB",
"PBRKPBS",
"PEOR",
"PEORS",
"PNAND",
"PNANDS",
"PNOR",
"PNORS",
"PORN",
"PORNS",
"PORR",
"PORRS",
"PPFALSE",
"PPFIRST",
"PPNEXT",
"PPTEST",
"PPTRUE",
"PPUNPKHI",
"PPUNPKLO",
"PRDFFR",
"PRDFFRS",
"PREV",
"PSEL",
"PTRN1",
"PTRN2",
"PUZP1",
"PUZP2",
"PWRFFR",
"PZIP1",
"PZIP2",
"SETFFR",
"ZABS",
"ZADCLB",
"ZADCLT",
"ZADD",
"ZADDHNB",
"ZADDHNT",
"ZADDP",
"ZADDPT",
"ZADDQP",
"ZADDQV",
"ZADDSUBP",
"ZAESD",
"ZAESE",
"ZAESIMC",
"ZAESMC",
"ZAND",
"ZANDQV",
"ZASR",
"ZASRR",
"ZBCAX",
"ZBDEP",
"ZBEXT",
"ZBF1CVT",
"ZBF1CVTLT",
"ZBF2CVT",
"ZBF2CVTLT",
"ZBFADD",
"ZBFCLAMP",
"ZBFCVT",
"ZBFCVTNT",
"ZBFDOT",
"ZBFMAX",
"ZBFMAXNM",
"ZBFMIN",
"ZBFMINNM",
"ZBFMLA",
"ZBFMLALB",
"ZBFMLALT",
"ZBFMLS",
"ZBFMLSLB",
"ZBFMLSLT",
"ZBFMMLA",
"ZBFMUL",
"ZBFSCALE",
"ZBFSUB",
"ZBGRP",
"ZBIC",
"ZBSL",
"ZBSL1N",
"ZBSL2N",
"ZCLASTA",
"ZCLASTB",
"ZCLS",
"ZCLZ",
"ZCMPEQ",
"ZCMPGE",
"ZCMPGT",
"ZCMPHI",
"ZCMPHS",
"ZCMPLE",
"ZCMPLO",
"ZCMPLS",
"ZCMPLT",
"ZCMPNE",
"ZCNOT",
"ZCNT",
"ZCOMPACT",
"ZDECP",
"ZEOR",
"ZEOR3",
"ZEORBT",
"ZEORQV",
"ZEORTB",
"ZEXPAND",
"ZF1CVT",
"ZF1CVTLT",
"ZF2CVT",
"ZF2CVTLT",
"ZFABD",
"ZFABS",
"ZFACGE",
"ZFACGT",
"ZFADD",
"ZFADDP",
"ZFADDQV",
"ZFAMAX",
"ZFAMIN",
"ZFCLAMP",
"ZFCMEQ",
"ZFCMGE",
"ZFCMGT",
"ZFCMNE",
"ZFCMUO",
"ZFCVT",
"ZFCVTLT",
"ZFCVTNT",
"ZFCVTX",
"ZFCVTXNT",
"ZFCVTZS",
"ZFCVTZU",
"ZFDIV",
"ZFDIVR",
"ZFDOT",
"ZFEXPA",
"ZFLOGB",
"ZFMAD",
"ZFMAX",
"ZFMAXNM",
"ZFMAXNMP",
"ZFMAXNMQV",
"ZFMAXP",
"ZFMAXQV",
"ZFMIN",
"ZFMINNM",
"ZFMINNMP",
"ZFMINNMQV",
"ZFMINP",
"ZFMINQV",
"ZFMLA",
"ZFMLALB",
"ZFMLALLBB",
"ZFMLALLBT",
"ZFMLALLTB",
"ZFMLALLTT",
"ZFMLALT",
"ZFMLS",
"ZFMLSLB",
"ZFMLSLT",
"ZFMMLA",
"ZFMSB",
"ZFMUL",
"ZFMULX",
"ZFNEG",
"ZFNMAD",
"ZFNMLA",
"ZFNMLS",
"ZFNMSB",
"ZFRECPE",
"ZFRECPS",
"ZFRECPX",
"ZFRINT32X",
"ZFRINT32Z",
"ZFRINT64X",
"ZFRINT64Z",
"ZFRINTA",
"ZFRINTI",
"ZFRINTM",
"ZFRINTN",
"ZFRINTP",
"ZFRINTX",
"ZFRINTZ",
"ZFRSQRTE",
"ZFRSQRTS",
"ZFSCALE",
"ZFSQRT",
"ZFSUB",
"ZFSUBR",
"ZFTSMUL",
"ZFTSSEL",
"ZHISTCNT",
"ZHISTSEG",
"ZINCP",
"ZLSL",
"ZLSLR",
"ZLSR",
"ZLSRR",
"ZMAD",
"ZMADPT",
"ZMATCH",
"ZMLA",
"ZMLAPT",
"ZMLS",
"ZMOVPRFX",
"ZMSB",
"ZMUL",
"ZNBSL",
"ZNEG",
"ZNMATCH",
"ZNOT",
"ZORQV",
"ZORR",
"ZPMOV",
"ZPMUL",
"ZPMULLB",
"ZPMULLT",
"ZRADDHNB",
"ZRADDHNT",
"ZRAX1",
"ZRBIT",
"ZREV",
"ZREVB",
"ZREVD",
"ZREVH",
"ZREVW",
"ZRSUBHNB",
"ZRSUBHNT",
"ZSABA",
"ZSABAL",
"ZSABALB",
"ZSABALT",
"ZSABD",
"ZSABDLB",
"ZSABDLT",
"ZSADALP",
"ZSADDLB",
"ZSADDLBT",
"ZSADDLT",
"ZSADDWB",
"ZSADDWT",
"ZSBCLB",
"ZSBCLT",
"ZSCLAMP",
"ZSCVTF",
"ZSCVTFLT",
"ZSDIV",
"ZSDIVR",
"ZSDOT",
"ZSEL",
"ZSHADD",
"ZSHSUB",
"ZSHSUBR",
"ZSM4E",
"ZSM4EKEY",
"ZSMAX",
"ZSMAXP",
"ZSMAXQV",
"ZSMIN",
"ZSMINP",
"ZSMINQV",
"ZSMLALB",
"ZSMLALT",
"ZSMLSLB",
"ZSMLSLT",
"ZSMMLA",
"ZSMULH",
"ZSMULLB",
"ZSMULLT",
"ZSPLICE",
"ZSQABS",
"ZSQADD",
"ZSQDECP",
"ZSQDMLALB",
"ZSQDMLALBT",
"ZSQDMLALT",
"ZSQDMLSLB",
"ZSQDMLSLBT",
"ZSQDMLSLT",
"ZSQDMULH",
"ZSQDMULLB",
"ZSQDMULLT",
"ZSQINCP",
"ZSQNEG",
"ZSQRDMLAH",
"ZSQRDMLSH",
"ZSQRDMULH",
"ZSQRSHL",
"ZSQRSHLR",
"ZSQSHL",
"ZSQSHLR",
"ZSQSUB",
"ZSQSUBR",
"ZSQXTNB",
"ZSQXTNT",
"ZSQXTUNB",
"ZSQXTUNT",
"ZSRHADD",
"ZSRSHL",
"ZSRSHLR",
"ZSSUBLB",
"ZSSUBLBT",
"ZSSUBLT",
"ZSSUBLTB",
"ZSSUBWB",
"ZSSUBWT",
"ZSUB",
"ZSUBHNB",
"ZSUBHNT",
"ZSUBP",
"ZSUBPT",
"ZSUBR",
"ZSUNPKHI",
"ZSUNPKLO",
"ZSUQADD",
"ZSXTB",
"ZSXTH",
"ZSXTW",
"ZTBX",
"ZTBXQ",
"ZTRN1",
"ZTRN2",
"ZUABA",
"ZUABAL",
"ZUABALB",
"ZUABALT",
"ZUABD",
"ZUABDLB",
"ZUABDLT",
"ZUADALP",
"ZUADDLB",
"ZUADDLT",
"ZUADDWB",
"ZUADDWT",
"ZUCLAMP",
"ZUCVTF",
"ZUCVTFLT",
"ZUDIV",
"ZUDIVR",
"ZUDOT",
"ZUHADD",
"ZUHSUB",
"ZUHSUBR",
"ZUMAX",
"ZUMAXP",
"ZUMAXQV",
"ZUMIN",
"ZUMINP",
"ZUMINQV",
"ZUMLALB",
"ZUMLALT",
"ZUMLSLB",
"ZUMLSLT",
"ZUMMLA",
"ZUMULH",
"ZUMULLB",
"ZUMULLT",
"ZUQADD",
"ZUQDECP",
"ZUQINCP",
"ZUQRSHL",
"ZUQRSHLR",
"ZUQSHL",
"ZUQSHLR",
"ZUQSUB",
"ZUQSUBR",
"ZUQXTNB",
"ZUQXTNT",
"ZURECPE",
"ZURHADD",
"ZURSHL",
"ZURSHLR",
"ZURSQRTE",
"ZUSDOT",
"ZUSMMLA",
"ZUSQADD",
"ZUSUBLB",
"ZUSUBLT",
"ZUSUBWB",
"ZUSUBWT",
"ZUUNPKHI",
"ZUUNPKLO",
"ZUXTB",
"ZUXTH",
"ZUXTW",
"ZUZP1",
"ZUZP2",
"ZUZPQ1",
"ZUZPQ2",
"ZZIP1",
"ZZIP2",
"ZZIPQ1",
"ZZIPQ2",
"LAST",
}
func init() {
Anames = append(Anames, sveAnames...)
}

72
src/cmd/internal/obj/arm64/asm7.go
View File

@@ -196,7 +196,7 @@ var atomicCASP = map[obj.As]uint32{
ACASPW: 0<<30 | 0x41<<21 | 0x1f<<10,
}
var oprange [ALAST & obj.AMask][]Optab
var oprange [obj.AllowedOpCodes][]Optab
var xcmp [C_NCLASS][C_NCLASS]bool
@@ -2183,7 +2183,23 @@ func (c *ctxt7) aclass(a *obj.Addr) int {
return C_GOK
}
// SVE instructions, type 127 is reserved for SVE instructions.
// All SVE instructions are sized 4 bytes.
var sveOptab = Optab{0, C_GOK, C_GOK, C_GOK, C_GOK, C_GOK, 127, 4, 0, 0, 0}
func isSVE(as obj.As) bool {
// A64 opcodes are prefixed with AZ or AP for SVE/SVE2
// In goops_gen.go they are defined starting from ASVESTART + 1.
return as > ASVESTART
}
func (c *ctxt7) oplook(p *obj.Prog) *Optab {
if isSVE(p.As) {
// All SVE instructions are in the Insts table.
// Matching happens in asmout.
return &sveOptab
}
a1 := int(p.Optab)
if a1 != 0 {
return &optab[a1-1]
@@ -5808,6 +5824,22 @@ func (c *ctxt7) asmout(p *obj.Prog, out []uint32) (count int) {
c.ctxt.Diag("illegal argument: %v\n", p)
break
}
case 127:
// Generic SVE instruction encoding
matched := false
groupIdx := int(p.As - ASVESTART - 1)
if groupIdx >= 0 && groupIdx < len(insts) {
for _, inst := range insts[groupIdx] {
if bin, ok := inst.tryEncode(p); ok {
o1 = bin
matched = true
break
}
}
}
if !matched {
c.ctxt.Diag("illegal combination from SVE: %v", p)
}
}
out[0] = o1
out[1] = o2
@@ -7921,6 +7953,44 @@ func EncodeRegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount,
return errors.New("unsupported general register extension type: " + ext)
}
} else if REG_Z0 <= reg && reg <= REG_Z31 {
var arng int
switch ext {
case "B":
arng = ARNG_B
case "H":
arng = ARNG_H
case "S":
arng = ARNG_S
case "D":
arng = ARNG_D
case "Q":
arng = ARNG_Q
default:
return errors.New("invalid Z register arrangement: " + ext)
}
a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5)
} else if REG_P0 <= reg && reg <= REG_PN15 {
var arng int
switch ext {
case "B":
arng = ARNG_B
case "H":
arng = ARNG_H
case "S":
arng = ARNG_S
case "D":
arng = ARNG_D
case "Q":
arng = ARNG_Q
case "Z":
arng = PRED_Z
case "M":
arng = PRED_M
default:
return errors.New("invalid P register arrangement: " + ext)
}
a.Reg = REG_PARNGZM + (reg & 31) + int16((arng&15)<<5)
} else if reg <= REG_V31 && reg >= REG_V0 {
switch ext {
case "B8":

877
src/cmd/internal/obj/arm64/encoding_gen.go Normal file
View File

@@ -0,0 +1,877 @@
// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'.
package arm64
const (
enc_NIL component = iota
enc_tszh_tszl
enc_M
enc_PNd
enc_Pd
enc_Pdm
enc_Pdn
enc_Pg
enc_Pm
enc_Pn
enc_Pv
enc_Vd
enc_Za
enc_Zd
enc_Zda
enc_Zdn
enc_Zk
enc_Zm
enc_Zn
enc_size
enc_size0
enc_sz
)
// encodeArngBCheck is the implementation of the following encoding logic:
// Check this is a B arrangement
func encodeArngBCheck(v uint32) (uint32, bool) {
if v == ARNG_B {
return 0, true
}
return 0, false
}
// encodeArngDCheck is the implementation of the following encoding logic:
// Check this is a D arrangement
func encodeArngDCheck(v uint32) (uint32, bool) {
if v == ARNG_D {
return 0, true
}
return 0, false
}
// encodeArngHCheck is the implementation of the following encoding logic:
// Check this is a H arrangement
func encodeArngHCheck(v uint32) (uint32, bool) {
if v == ARNG_H {
return 0, true
}
return 0, false
}
// encodeArngQCheck is the implementation of the following encoding logic:
// Check this is a Q arrangement
func encodeArngQCheck(v uint32) (uint32, bool) {
if v == ARNG_Q {
return 0, true
}
return 0, false
}
// encodeArngSCheck is the implementation of the following encoding logic:
// Check this is a S arrangement
func encodeArngSCheck(v uint32) (uint32, bool) {
if v == ARNG_S {
return 0, true
}
return 0, false
}
// encodeMergePredCheck is the implementation of the following encoding logic:
// Check this is a merging predication
func encodeMergePredCheck(v uint32) (uint32, bool) {
if v == PRED_M {
return 0, true
}
return 0, false
}
// encodeZeroPredCheck is the implementation of the following encoding logic:
// Check this is a zeroing predication
func encodeZeroPredCheck(v uint32) (uint32, bool) {
if v == PRED_Z {
return 0, true
}
return 0, false
}
// encodeSzByteHalfword is the implementation of the following encoding logic:
// For the "Byte and halfword" variant: is the size specifier,
// sz <T>
// 0 B
// 1 H
// bit range mappings:
// sz: [22:23)
func encodeSzByteHalfword(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0, true
case ARNG_H:
return 1 << 22, true
}
return 0, false
}
// encodeSizeByteMergeZero is the implementation of the following encoding logic:
// For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier,
// size <T>
// 00 RESERVED
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeByteMergeZero(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSize0HalfwordMergeZero is the implementation of the following encoding logic:
// For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier,
// size[0] <T>
// 0 S
// 1 D
// bit range mappings:
// size: [22:23)
func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0, true
case ARNG_D:
return 1 << 22, true
}
return 0, false
}
// encodeSzWordDoubleword is the implementation of the following encoding logic:
// For the "Word and doubleword" variant: is the size specifier,
// sz <T>
// 0 S
// 1 D
// bit range mappings:
// sz: [22:23)
func encodeSzWordDoubleword(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0, true
case ARNG_D:
return 1 << 22, true
}
return 0, false
}
// encodeSize16B8H4S2D is the implementation of the following encoding logic:
// Is an arrangement specifier,
// size <T>
// 00 16B
// 01 8H
// 10 4S
// 11 2D
// bit range mappings:
// size: [22:24)
func encodeSize16B8H4S2D(v uint32) (uint32, bool) {
switch v {
case ARNG_16B:
return 0, true
case ARNG_8H:
return 1 << 22, true
case ARNG_4S:
return 2 << 22, true
case ARNG_2D:
return 3 << 22, true
}
return 0, false
}
// encodeSize8H4S2D is the implementation of the following encoding logic:
// Is an arrangement specifier,
// size <T>
// 00 RESERVED
// 01 8H
// 10 4S
// 11 2D
// bit range mappings:
// size: [22:24)
func encodeSize8H4S2D(v uint32) (uint32, bool) {
switch v {
case ARNG_8H:
return 1 << 22, true
case ARNG_4S:
return 2 << 22, true
case ARNG_2D:
return 3 << 22, true
}
return 0, false
}
// encodeVd is the implementation of the following encoding logic:
// Is the name of the destination SIMD&FP register, encoded in the "Vd" field.
// bit range mappings:
// Vd: [0:5)
func encodeVd(v uint32) (uint32, bool) {
return v, true
}
// encodePNd is the implementation of the following encoding logic:
// Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
// bit range mappings:
// PNd: [0:3)
func encodePNd(v uint32) (uint32, bool) {
if v >= 24 && v <= 31 {
// PN registers starts from 16.
return v - 24, true
}
return 0, false
}
// encodePd is the implementation of the following encoding logic:
// Is the name of the destination scalable predicate register, encoded in the "Pd" field.
// bit range mappings:
// Pd: [0:4)
func encodePd(v uint32) (uint32, bool) {
return v, true
}
// encodeZd is the implementation of the following encoding logic:
// Is the name of the destination scalable vector register, encoded in the "Zd" field.
// bit range mappings:
// Zd: [0:5)
func encodeZd(v uint32) (uint32, bool) {
return v, true
}
// encodePdnDest is the implementation of the following encoding logic:
// Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
// Pdn: [0:4)
func encodePdnDest(v uint32) (uint32, bool) {
return v, true
}
// encodeZdnDest is the implementation of the following encoding logic:
// Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
// bit range mappings:
// Zdn: [0:5)
func encodeZdnDest(v uint32) (uint32, bool) {
return v, true
}
// encodePn59 is the implementation of the following encoding logic:
// Is the name of the first source scalable predicate register, encoded in the "Pn" field.
// bit range mappings:
// Pn: [5:9)
func encodePn59(v uint32) (uint32, bool) {
return v << 5, true
}
// encodeZn510 is the implementation of the following encoding logic:
// Is the name of the first source scalable vector register, encoded in the "Zn" field.
// bit range mappings:
// Zn: [5:10)
func encodeZn510(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePg1013 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
// bit range mappings:
// Pg: [10:13)
func encodePg1013(v uint32) (uint32, bool) {
if v <= 7 {
return v << 10, true
}
return 0, false
}
// encodePg1014 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
// bit range mappings:
// Pg: [10:14)
func encodePg1014(v uint32) (uint32, bool) {
return v << 10, true
}
// encodePg59 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
// bit range mappings:
// Pg: [5:9)
func encodePg59(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePdmDest is the implementation of the following encoding logic:
// Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
// bit range mappings:
// Pdm: [0:4)
func encodePdmDest(v uint32) (uint32, bool) {
return v, true
}
// encodeZdaDest is the implementation of the following encoding logic:
// Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.
// bit range mappings:
// Zda: [0:5)
func encodeZdaDest(v uint32) (uint32, bool) {
return v, true
}
// encodePm1620 is the implementation of the following encoding logic:
// Is the name of the second source scalable predicate register, encoded in the "Pm" field.
// bit range mappings:
// Pm: [16:20)
func encodePm1620(v uint32) (uint32, bool) {
return v << 16, true
}
// encodeZm1621 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:21)
func encodeZm1621(v uint32) (uint32, bool) {
return v << 16, true
}
// encodeZm510 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [5:10)
func encodeZm510(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePdnSrcDst is the implementation of the following encoding logic:
// Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
// Pdn: [0:4)
func encodePdnSrcDst(v uint32) (uint32, bool) {
return v, true
}
// encodeZdnSrcDst is the implementation of the following encoding logic:
// Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
// bit range mappings:
// Zdn: [0:5)
func encodeZdnSrcDst(v uint32) (uint32, bool) {
return v, true
}
// encodePm59v1 is the implementation of the following encoding logic:
// Is the name of the source scalable predicate register, encoded in the "Pm" field.
// bit range mappings:
// Pm: [5:9)
func encodePm59v1(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePn59v2 is the implementation of the following encoding logic:
// Is the name of the source scalable predicate register, encoded in the "Pn" field.
// bit range mappings:
// Pn: [5:9)
func encodePn59v2(v uint32) (uint32, bool) {
return v << 5, true
}
// encodeZn510Src is the implementation of the following encoding logic:
// Is the name of the source scalable vector register, encoded in the "Zn" field.
// bit range mappings:
// Zn: [5:10)
func encodeZn510Src(v uint32) (uint32, bool) {
return v << 5, true
}
// encodeZda3RdSrcDst is the implementation of the following encoding logic:
// Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
// bit range mappings:
// Zda: [0:5)
func encodeZda3RdSrcDst(v uint32) (uint32, bool) {
return v, true
}
// encodeZa16213Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Za" field.
// bit range mappings:
// Za: [16:21)
func encodeZa16213Rd(v uint32) (uint32, bool) {
return v << 16, true
}
// encodeZa5103Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Za" field.
// bit range mappings:
// Za: [5:10)
func encodeZa5103Rd(v uint32) (uint32, bool) {
return v << 5, true
}
// encodeZk5103Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Zk" field.
// bit range mappings:
// Zk: [5:10)
func encodeZk5103Rd(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePv1013 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register P0-P7, encoded in the "Pv" field.
// bit range mappings:
// Pv: [10:13)
func encodePv1013(v uint32) (uint32, bool) {
return v << 10, true
}
// encodePv1014 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register, encoded in the "Pv" field.
// bit range mappings:
// Pv: [10:14)
func encodePv1014(v uint32) (uint32, bool) {
return v << 10, true
}
// encodePv59 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register, encoded in the "Pv" field.
// bit range mappings:
// Pv: [5:9)
func encodePv59(v uint32) (uint32, bool) {
return v << 5, true
}
// encodePredQualM1617 is the implementation of the following encoding logic:
// Is the predication qualifier,
// M <ZM>
// 0 Z
// 1 M
// bit range mappings:
// M: [16:17)
func encodePredQualM1617(v uint32) (uint32, bool) {
switch v {
case PRED_Z:
return 0, true
case PRED_M:
return 1 << 16, true
}
return 0, false
}
// encodePredQualM45 is the implementation of the following encoding logic:
// Is the predication qualifier,
// M <ZM>
// 0 Z
// 1 M
// bit range mappings:
// M: [4:5)
func encodePredQualM45(v uint32) (uint32, bool) {
switch v {
case PRED_Z:
return 0, true
case PRED_M:
return 1 << 4, true
}
return 0, false
}
// encodeSizeBHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 B
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeBHSD2224(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0 << 22, true
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeBHS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 B
// 01 H
// 10 S
// 11 RESERVED
// bit range mappings:
// size: [22:24)
func encodeSizeBHS2224(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0 << 22, true
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
}
return 0, false
}
// encodeSizeBHS2224Offset1 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 RESERVED
// 01 B
// 10 H
// 11 S
// bit range mappings:
// size: [22:24)
func encodeSizeBHS2224Offset1(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 1 << 22, true
case ARNG_H:
return 2 << 22, true
case ARNG_S:
return 3 << 22, true
}
return 0, false
}
// encodeSizeHSD1315 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 RESERVED
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [13:15)
func encodeSizeHSD1315(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 13, true
case ARNG_S:
return 2 << 13, true
case ARNG_D:
return 3 << 13, true
}
return 0, false
}
// encodeSizeHSD1719 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 RESERVED
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [17:19)
func encodeSizeHSD1719(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 17, true
case ARNG_S:
return 2 << 17, true
case ARNG_D:
return 3 << 17, true
}
return 0, false
}
// encodeSizeHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 00 RESERVED
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeHSD2224(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeHSD2224No00 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeHSD2224No00(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeHD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <T>
// 01 H
// 1x D
// bit range mappings:
// size: [22:24)
func encodeSizeHD2224(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeTbBHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <Tb>
// 00 B
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeTbBHSD2224(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0 << 22, true
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeTbBHS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <Tb>
// 00 RESERVED
// 01 B
// 10 H
// 11 S
// bit range mappings:
// size: [22:24)
func encodeSizeTbBHS2224(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 1 << 22, true
case ARNG_H:
return 2 << 22, true
case ARNG_S:
return 3 << 22, true
}
return 0, false
}
// encodeSizeTbHSD2224Offset1 is the implementation of the following encoding logic:
// Is the size specifier,
// size <Tb>
// 00 RESERVED
// 01 H
// 10 S
// 11 D
// bit range mappings:
// size: [22:24)
func encodeSizeTbHSD2224Offset1(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 1 << 22, true
case ARNG_S:
return 2 << 22, true
case ARNG_D:
return 3 << 22, true
}
return 0, false
}
// encodeSizeTbBS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size <Tb>
// 01 B
// 1x S
// bit range mappings:
// size: [22:24)
func encodeSizeTbBS2224(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 1 << 22, true
case ARNG_S:
return 3 << 22, true
}
return 0, false
}
// encodeSize0BH2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0] <T>
// 0 B
// 1 H
// bit range mappings:
// size: [22:23)
func encodeSize0BH2223(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0 << 22, true
case ARNG_H:
return 1 << 22, true
}
return 0, false
}
// encodeSize0SD2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0] <T>
// 0 S
// 1 D
// bit range mappings:
// size: [22:23)
func encodeSize0SD2223(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0 << 22, true
case ARNG_D:
return 1 << 22, true
}
return 0, false
}
// encodeSize0TbBH2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0] <Tb>
// 0 B
// 1 H
// bit range mappings:
// size: [22:23)
func encodeSize0TbBH2223(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0 << 22, true
case ARNG_H:
return 1 << 22, true
}
return 0, false
}
// encodeSzSD1415 is the implementation of the following encoding logic:
// Is the size specifier,
// sz <T>
// 0 S
// 1 D
// bit range mappings:
// sz: [14:15)
func encodeSzSD1415(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0 << 14, true
case ARNG_D:
return 1 << 14, true
}
return 0, false
}
// encodeSzSD1718 is the implementation of the following encoding logic:
// Is the size specifier,
// sz <T>
// 0 S
// 1 D
// bit range mappings:
// sz: [17:18)
func encodeSzSD1718(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0 << 17, true
case ARNG_D:
return 1 << 17, true
}
return 0, false
}
// encodeSzSD2223 is the implementation of the following encoding logic:
// Is the size specifier,
// sz <T>
// 0 S
// 1 D
// bit range mappings:
// sz: [22:23)
func encodeSzSD2223(v uint32) (uint32, bool) {
switch v {
case ARNG_S:
return 0 << 22, true
case ARNG_D:
return 1 << 22, true
}
return 0, false
}
// encodeTszhTszlBHS is the implementation of the following encoding logic:
// Is the size specifier,
// tszh tszl <T>
// 0 00 RESERVED
// 0 01 B
// 0 10 H
// 0 11 RESERVED
// 1 00 S
// 1 01 RESERVED
// 1 1x RESERVED
// bit range mappings:
// tszh: [22:23)
// tszl: [19:21)
func encodeTszhTszlBHS(v uint32) (uint32, bool) {
switch v {
case ARNG_B:
return 0<<22 | 1<<19, true
case ARNG_H:
return 0<<22 | 2<<19, true
case ARNG_S:
return 1 << 22, true
}
return 0, false
}
// encodeTszhTszlTbHSD is the implementation of the following encoding logic:
// Is the size specifier,
// tszh tszl <Tb>
// 0 00 RESERVED
// 0 01 H
// 0 10 S
// 0 11 RESERVED
// 1 00 D
// 1 01 RESERVED
// 1 1x RESERVED
// bit range mappings:
// tszh: [22:23)
// tszl: [19:21)
func encodeTszhTszlTbHSD(v uint32) (uint32, bool) {
switch v {
case ARNG_H:
return 0<<22 | 1<<19, true
case ARNG_S:
return 0<<22 | 2<<19, true
case ARNG_D:
return 1 << 22, true
}
return 0, false
}
// encodeNoop is the implementation of the following encoding logic:
// No-op check, returns true
func encodeNoop(v uint32) (uint32, bool) {
return 0, true
}

413
src/cmd/internal/obj/arm64/goops_gen.go Normal file
View File

@@ -0,0 +1,413 @@
// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
package arm64
import "cmd/internal/obj"
const (
APAND obj.As = ASVESTART + 1 + iota
APANDS
APBIC
APBICS
APBRKA
APBRKAS
APBRKB
APBRKBS
APBRKN
APBRKNS
APBRKPA
APBRKPAS
APBRKPB
APBRKPBS
APEOR
APEORS
APNAND
APNANDS
APNOR
APNORS
APORN
APORNS
APORR
APORRS
APPFALSE
APPFIRST
APPNEXT
APPTEST
APPTRUE
APPUNPKHI
APPUNPKLO
APRDFFR
APRDFFRS
APREV
APSEL
APTRN1
APTRN2
APUZP1
APUZP2
APWRFFR
APZIP1
APZIP2
ASETFFR
AZABS
AZADCLB
AZADCLT
AZADD
AZADDHNB
AZADDHNT
AZADDP
AZADDPT
AZADDQP
AZADDQV
AZADDSUBP
AZAESD
AZAESE
AZAESIMC
AZAESMC
AZAND
AZANDQV
AZASR
AZASRR
AZBCAX
AZBDEP
AZBEXT
AZBF1CVT
AZBF1CVTLT
AZBF2CVT
AZBF2CVTLT
AZBFADD
AZBFCLAMP
AZBFCVT
AZBFCVTNT
AZBFDOT
AZBFMAX
AZBFMAXNM
AZBFMIN
AZBFMINNM
AZBFMLA
AZBFMLALB
AZBFMLALT
AZBFMLS
AZBFMLSLB
AZBFMLSLT
AZBFMMLA
AZBFMUL
AZBFSCALE
AZBFSUB
AZBGRP
AZBIC
AZBSL
AZBSL1N
AZBSL2N
AZCLASTA
AZCLASTB
AZCLS
AZCLZ
AZCMPEQ
AZCMPGE
AZCMPGT
AZCMPHI
AZCMPHS
AZCMPLE
AZCMPLO
AZCMPLS
AZCMPLT
AZCMPNE
AZCNOT
AZCNT
AZCOMPACT
AZDECP
AZEOR
AZEOR3
AZEORBT
AZEORQV
AZEORTB
AZEXPAND
AZF1CVT
AZF1CVTLT
AZF2CVT
AZF2CVTLT
AZFABD
AZFABS
AZFACGE
AZFACGT
AZFADD
AZFADDP
AZFADDQV
AZFAMAX
AZFAMIN
AZFCLAMP
AZFCMEQ
AZFCMGE
AZFCMGT
AZFCMNE
AZFCMUO
AZFCVT
AZFCVTLT
AZFCVTNT
AZFCVTX
AZFCVTXNT
AZFCVTZS
AZFCVTZU
AZFDIV
AZFDIVR
AZFDOT
AZFEXPA
AZFLOGB
AZFMAD
AZFMAX
AZFMAXNM
AZFMAXNMP
AZFMAXNMQV
AZFMAXP
AZFMAXQV
AZFMIN
AZFMINNM
AZFMINNMP
AZFMINNMQV
AZFMINP
AZFMINQV
AZFMLA
AZFMLALB
AZFMLALLBB
AZFMLALLBT
AZFMLALLTB
AZFMLALLTT
AZFMLALT
AZFMLS
AZFMLSLB
AZFMLSLT
AZFMMLA
AZFMSB
AZFMUL
AZFMULX
AZFNEG
AZFNMAD
AZFNMLA
AZFNMLS
AZFNMSB
AZFRECPE
AZFRECPS
AZFRECPX
AZFRINT32X
AZFRINT32Z
AZFRINT64X
AZFRINT64Z
AZFRINTA
AZFRINTI
AZFRINTM
AZFRINTN
AZFRINTP
AZFRINTX
AZFRINTZ
AZFRSQRTE
AZFRSQRTS
AZFSCALE
AZFSQRT
AZFSUB
AZFSUBR
AZFTSMUL
AZFTSSEL
AZHISTCNT
AZHISTSEG
AZINCP
AZLSL
AZLSLR
AZLSR
AZLSRR
AZMAD
AZMADPT
AZMATCH
AZMLA
AZMLAPT
AZMLS
AZMOVPRFX
AZMSB
AZMUL
AZNBSL
AZNEG
AZNMATCH
AZNOT
AZORQV
AZORR
AZPMOV
AZPMUL
AZPMULLB
AZPMULLT
AZRADDHNB
AZRADDHNT
AZRAX1
AZRBIT
AZREV
AZREVB
AZREVD
AZREVH
AZREVW
AZRSUBHNB
AZRSUBHNT
AZSABA
AZSABAL
AZSABALB
AZSABALT
AZSABD
AZSABDLB
AZSABDLT
AZSADALP
AZSADDLB
AZSADDLBT
AZSADDLT
AZSADDWB
AZSADDWT
AZSBCLB
AZSBCLT
AZSCLAMP
AZSCVTF
AZSCVTFLT
AZSDIV
AZSDIVR
AZSDOT
AZSEL
AZSHADD
AZSHSUB
AZSHSUBR
AZSM4E
AZSM4EKEY
AZSMAX
AZSMAXP
AZSMAXQV
AZSMIN
AZSMINP
AZSMINQV
AZSMLALB
AZSMLALT
AZSMLSLB
AZSMLSLT
AZSMMLA
AZSMULH
AZSMULLB
AZSMULLT
AZSPLICE
AZSQABS
AZSQADD
AZSQDECP
AZSQDMLALB
AZSQDMLALBT
AZSQDMLALT
AZSQDMLSLB
AZSQDMLSLBT
AZSQDMLSLT
AZSQDMULH
AZSQDMULLB
AZSQDMULLT
AZSQINCP
AZSQNEG
AZSQRDMLAH
AZSQRDMLSH
AZSQRDMULH
AZSQRSHL
AZSQRSHLR
AZSQSHL
AZSQSHLR
AZSQSUB
AZSQSUBR
AZSQXTNB
AZSQXTNT
AZSQXTUNB
AZSQXTUNT
AZSRHADD
AZSRSHL
AZSRSHLR
AZSSUBLB
AZSSUBLBT
AZSSUBLT
AZSSUBLTB
AZSSUBWB
AZSSUBWT
AZSUB
AZSUBHNB
AZSUBHNT
AZSUBP
AZSUBPT
AZSUBR
AZSUNPKHI
AZSUNPKLO
AZSUQADD
AZSXTB
AZSXTH
AZSXTW
AZTBX
AZTBXQ
AZTRN1
AZTRN2
AZUABA
AZUABAL
AZUABALB
AZUABALT
AZUABD
AZUABDLB
AZUABDLT
AZUADALP
AZUADDLB
AZUADDLT
AZUADDWB
AZUADDWT
AZUCLAMP
AZUCVTF
AZUCVTFLT
AZUDIV
AZUDIVR
AZUDOT
AZUHADD
AZUHSUB
AZUHSUBR
AZUMAX
AZUMAXP
AZUMAXQV
AZUMIN
AZUMINP
AZUMINQV
AZUMLALB
AZUMLALT
AZUMLSLB
AZUMLSLT
AZUMMLA
AZUMULH
AZUMULLB
AZUMULLT
AZUQADD
AZUQDECP
AZUQINCP
AZUQRSHL
AZUQRSHLR
AZUQSHL
AZUQSHLR
AZUQSUB
AZUQSUBR
AZUQXTNB
AZUQXTNT
AZURECPE
AZURHADD
AZURSHL
AZURSHLR
AZURSQRTE
AZUSDOT
AZUSMMLA
AZUSQADD
AZUSUBLB
AZUSUBLT
AZUSUBWB
AZUSUBWT
AZUUNPKHI
AZUUNPKLO
AZUXTB
AZUXTH
AZUXTW
AZUZP1
AZUZP2
AZUZPQ1
AZUZPQ2
AZZIP1
AZZIP2
AZZIPQ1
AZZIPQ2
ALAST
)

188
src/cmd/internal/obj/arm64/inst.go Normal file
View File

@@ -0,0 +1,188 @@
// Copyright 2026 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
package arm64
import (
"cmd/internal/obj"
"fmt"
"iter"
)
// instEncoder represents an instruction encoder.
type instEncoder struct {
goOp obj.As // Go opcode mnemonic
fixedBits uint32 // Known bits
args []operand // Operands, in Go order
}
type varBits struct {
// The low and high bit index in the binary encoding, exclusive on hi
lo, hi int
encoded bool // If true then its value is already encoded
bits uint32
}
// component is the component of an binary encoding.
// e.g. for operand <Zda>.<T>, <T>'s encoding function might be described as:
//
// For the "Byte and halfword" variant: is the size specifier,
// sz <T>
// 0 B
// 1 H
// bit range mappings:
// sz: [22:23)
//
// Then sz is the component of the binary encoding.
type component uint16
type elemEncoder struct {
fn func(uint32) (uint32, bool)
// comp is the component of the binary encoding.
comp component
}
// operand is the operand type of an instruction.
type operand struct {
class AClass // Operand class, register, constant, memory operation etc.
// The elements that this operand includes, this only includes the encoding-related parts
// They are represented as a list of pointers to the encoding functions.
// The first returned value is the encoded binary, the second is the ok signal.
// The encoding functions return the ok signal for deduplication purposes:
// For example:
// SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
// SDOT <Zda>.H, <Zn>.B, <Zm>.B
// SDOT <Zda>.S, <Zn>.H, <Zm>.H
//
// <T> and <Tb> are specified in the encoding text, that there is a constraint "T = 4*Tb".
// We don't know this fact by looking at the encoding format solely, without this information
// the first encoding domain entails the other 2. And at instruction matching phase we simply
// cannot deduplicate them. So we defer this deduplication to the encoding phase.
// We need the ok signal with [elemEncoder.comp] field to deduplicate them.
elemEncoders []elemEncoder
}
// opsInProg returns an iterator over the operands ([Addr]) of p
func opsInProg(p *obj.Prog) iter.Seq[*obj.Addr] {
return func(yield func(*obj.Addr) bool) {
// Go order: From, Reg, RestArgs..., To
// For SVE, Reg is unused as it's so common that registers have arrangements.
if p.From.Type != obj.TYPE_NONE {
if !yield(&p.From) {
return
}
}
for j := range p.RestArgs {
if !yield(&p.RestArgs[j].Addr) {
return
}
}
if p.To.Type != obj.TYPE_NONE {
if !yield(&p.To) {
return
}
}
}
}
// aclass returns the AClass of an Addr.
func aclass(a *obj.Addr) AClass {
if a.Type == obj.TYPE_REG {
if a.Reg >= REG_Z0 && a.Reg <= REG_Z31 {
return AC_ZREG
}
if a.Reg >= REG_P0 && a.Reg <= REG_P15 {
return AC_PREG
}
if a.Reg >= REG_ARNG && a.Reg < REG_ELEM {
return AC_ARNG
}
if a.Reg >= REG_ZARNG && a.Reg < REG_PARNGZM {
return AC_ARNG
}
if a.Reg >= REG_PARNGZM && a.Reg < REG_PARNGZM_END {
switch (a.Reg >> 5) & 15 {
case PRED_M, PRED_Z:
return AC_PREGZM
default:
return AC_ARNG
}
}
}
panic("unknown AClass")
}
// addrComponent returns the binary (component) of the stored element in a at index, for operand
// of type aclass.
//
// For example, for operand of type AC_ARNG, it has 2 permissible components (identified by index)
// 0. register: <reg>
// 1. arrangement: <T>
//
// They are stored in a.Reg as:
//
// reg | (arrangement << 5)
//
// More details are in the comments in the switch cases of this function.
func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
switch acl {
// AClass: AC_ARNG, AC_PREG, AC_PREGZ, AC_PREGM, AC_ZREG
// GNU mnemonic: <reg>.<T> Or <reg>/<T> (T is M or Z)
// Go mnemonic:
// reg.<T>
// Encoding:
// Type = TYPE_REG
// Reg = reg | (arrangement or predication << 5)
case AC_ARNG, AC_PREG, AC_PREGZM, AC_ZREG:
switch index {
case 0:
return uint32(a.Reg & 31)
case 1:
return uint32((a.Reg >> 5) & 15)
default:
panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
}
}
// TODO: handle more AClasses.
panic(fmt.Errorf("unknown AClass %d", acl))
}
// tryEncode tries to encode p with i, it returns the encoded binary and ok signal.
func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
bin := i.fixedBits
// Some elements are encoded in the same component, they need to be equal.
// For example { <Zn1>.<Tb>-<Zn2>.<Tb> }.
// The 2 instances of <Tb> must encode to the same value.
encoded := map[component]uint32{}
opIdx := 0
for addr := range opsInProg(p) {
if opIdx >= len(i.args) {
return 0, false
}
op := i.args[opIdx]
opIdx++
acl := aclass(addr)
if acl != op.class {
return 0, false
}
for i, enc := range op.elemEncoders {
val := addrComponent(addr, acl, i)
if b, ok := enc.fn(val); ok {
bin |= b
if _, ok := encoded[enc.comp]; ok && b != encoded[enc.comp] {
return 0, false
}
if enc.comp != enc_NIL {
encoded[enc.comp] = b
}
} else {
return 0, false
}
}
}
if opIdx != len(i.args) {
return 0, false
}
return bin, true
}

6307
src/cmd/internal/obj/arm64/inst_gen.go Normal file
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File diff suppressed because it is too large Load Diff

25
src/cmd/internal/obj/arm64/list7.go
View File

@@ -90,6 +90,12 @@ func arrange(a int) string {
return "D"
case ARNG_1Q:
return "Q1"
case ARNG_Q:
return "Q"
case PRED_M:
return "M"
case PRED_Z:
return "Z"
default:
return ""
}
@@ -109,6 +115,12 @@ func rconv(r int) string {
return fmt.Sprintf("F%d", r-REG_F0)
case REG_V0 <= r && r <= REG_V31:
return fmt.Sprintf("V%d", r-REG_V0)
case REG_Z0 <= r && r <= REG_Z31:
return fmt.Sprintf("Z%d", r-REG_Z0)
case REG_P0 <= r && r <= REG_P15:
return fmt.Sprintf("P%d", r-REG_P0)
case REG_PN0 <= r && r <= REG_PN15:
return fmt.Sprintf("PN%d", r-REG_PN0)
case r == REGSP:
return "RSP"
case REG_UXTB <= r && r < REG_UXTH:
@@ -166,6 +178,19 @@ func rconv(r int) string {
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
case REG_ELEM <= r && r < REG_ELEM_END:
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
case REG_ZARNG <= r && r < REG_PARNGZM:
return fmt.Sprintf("Z%d.%s", r&31, arrange((r>>5)&15))
case REG_PARNGZM <= r && r < REG_PARNGZM_END:
// SVE predicate register with arrangement.
// Pn.<T> or Pn/M, Pn/Z.
arng := (r >> 5) & 31
suffix := arrange(arng)
reg := r & 31
if reg >= 16 {
// PN registers
return fmt.Sprintf("PN%d.%s", reg-16, suffix)
}
return fmt.Sprintf("P%d.%s", reg, suffix)
}
// Return system register name.
name, _, _ := SysRegEnc(int16(r))

12
src/cmd/internal/obj/util.go
View File

@@ -514,12 +514,12 @@ const (
RBaseAMD64 = 2 * 1024
RBaseARM = 3 * 1024
RBasePPC64 = 4 * 1024 // range [4k, 8k)
RBaseARM64 = 8 * 1024 // range [8k, 13k)
RBaseMIPS = 13 * 1024 // range [13k, 14k)
RBaseS390X = 14 * 1024 // range [14k, 15k)
RBaseRISCV = 15 * 1024 // range [15k, 16k)
RBaseWasm = 16 * 1024
RBaseLOONG64 = 19 * 1024 // range [19K, 22k)
RBaseARM64 = 8 * 1024 // range [8k, 18k)
RBaseMIPS = 18 * 1024 // range [18k, 19k)
RBaseS390X = 19 * 1024 // range [19k, 20k)
RBaseRISCV = 20 * 1024 // range [20k, 21k)
RBaseWasm = 21 * 1024
RBaseLOONG64 = 22 * 1024 // range [22K, 25k)
)
// RegisterRegister binds a pretty-printer (Rconv) for register