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test/codegen: tighten bit related codegen tests on riscv64

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Ensure that loading the value of one is included and specify the actual
constants for various instructions. Avoid potential ambiguity with
instructions (e.g. use "AND " to avoid matching "ANDI").

Change-Id: I42707bd68fab9e12d984670e64a02ee93667f77c
Reviewed-on: https://go-review.googlesource.com/c/go/+/748920
Reviewed-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
This commit is contained in:
Joel Sing
2025-12-25 01:01:19 +11:00
parent e0c8676edd
commit 5cd4b35d73
1 changed files with 47 additions and 47 deletions
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94
test/codegen/bits.go
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@@ -16,21 +16,21 @@ func bitsCheckConstLeftShiftU64(a uint64) (n int) {
// amd64:"BTQ [$]63,"
// arm64:"TBNZ [$]63,"
// loong64:"MOVV [$]" "AND" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]-9223372036854775808," "AND " "BNEZ"
if a&(1<<63) != 0 {
return 1
}
// amd64:"BTQ [$]60,"
// arm64:"TBNZ [$]60,"
// loong64:"MOVV [$]" "AND" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]1152921504606846976," "AND " "BNEZ"
if a&(1<<60) != 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ [$]0,"
// loong64:"AND [$]1," "BEQ"
// riscv64:"ANDI" "BEQZ"
// riscv64:"ANDI [$]1," "BEQZ"
if a&(1<<0) != 0 {
return 1
}
@@ -41,49 +41,49 @@ func bitsCheckConstRightShiftU64(a [8]uint64) (n int) {
// amd64:"BTQ [$]63,"
// arm64:"LSR [$]63," "TBNZ [$]0,"
// loong64:"SRLV [$]63," "AND [$]1," "BNE"
// riscv64:"SRLI" "ANDI" "BNEZ"
// riscv64:"SRLI [$]63," "ANDI [$]1," "BNEZ"
if (a[0]>>63)&1 != 0 {
return 1
}
// amd64:"BTQ [$]63,"
// arm64:"LSR [$]63," "CBNZ"
// loong64:"SRLV [$]63," "BNE"
// riscv64:"SRLI" "BNEZ"
// riscv64:"SRLI [$]63," "BNEZ"
if a[1]>>63 != 0 {
return 1
}
// amd64:"BTQ [$]63,"
// arm64:"LSR [$]63," "CBZ"
// loong64:"SRLV [$]63," "BEQ"
// riscv64:"SRLI" "BEQZ"
// riscv64:"SRLI [$]63," "BEQZ"
if a[2]>>63 == 0 {
return 1
}
// amd64:"BTQ [$]60,"
// arm64:"LSR [$]60," "TBZ [$]0,"
// loong64:"SRLV [$]60," "AND [$]1," "BEQ"
// riscv64:"SRLI", "ANDI" "BEQZ"
// riscv64:"SRLI [$]60,", "ANDI [$]1," "BEQZ"
if (a[3]>>60)&1 == 0 {
return 1
}
// amd64:"BTL [$]1,"
// arm64:"LSR [$]1," "TBZ [$]0,"
// loong64:"SRLV [$]1," "AND [$]1," "BEQ"
// riscv64:"SRLI" "ANDI" "BEQZ"
// riscv64:"SRLI [$]1," "ANDI [$]1," "BEQZ"
if (a[4]>>1)&1 == 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ [$]0," -"LSR"
// loong64:"AND [$]1," "BEQ" -"SRLV"
// riscv64:"ANDI" "BEQZ" -"SRLI"
// riscv64:"ANDI [$]1," "BEQZ" -"SRLI"
if (a[5]>>0)&1 == 0 {
return 1
}
// amd64:"BTL [$]7,"
// arm64:"LSR [$]5," "TBNZ [$]2,"
// loong64:"SRLV [$]5," "AND [$]4," "BNE"
// riscv64:"SRLI" "ANDI" "BNEZ"
// riscv64:"SRLI [$]5," "ANDI [$]4," "BNEZ"
if (a[6]>>5)&4 == 0 {
return 1
}
@@ -94,14 +94,14 @@ func bitsCheckVarU64(a, b uint64) (n int) {
// amd64:"BTQ"
// arm64:"MOVD [$]1," "LSL" "TST"
// loong64:"MOVV [$]1," "SLLV R" "AND" "BNE"
// riscv64:"ANDI [$]63," "SLL " "AND "
// riscv64:"ANDI [$]63," "MOV [$]1," "SLL " "AND "
if a&(1<<(b&63)) != 0 {
return 1
}
// amd64:"BTQ" -"BT. [$]0,"
// arm64:"LSR" "TBZ [$]0,"
// loong64:"SRLV" "AND [$]1," "BEQ"
// riscv64:"ANDI [$]63," "SRL" "ANDI [$]1,"
// riscv64:"ANDI [$]63," "SRL " "ANDI [$]1,"
if (b>>(a&63))&1 != 0 {
return 1
}
@@ -112,21 +112,21 @@ func bitsCheckMaskU64(a uint64) (n int) {
// amd64:"BTQ [$]63,"
// arm64:"TBNZ [$]63,"
// loong64:"MOVV [$]" "AND" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]-9223372036854775808" "AND " "BNEZ"
if a&0x8000000000000000 != 0 {
return 1
}
// amd64:"BTQ [$]59,"
// arm64:"TBNZ [$]59,"
// loong64:"MOVV [$]" "AND" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]576460752303423488" "AND " "BNEZ"
if a&0x800000000000000 != 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ [$]0,"
// loong64:"AND [$]1," "BEQ"
// riscv64:"ANDI" "BEQZ"
// riscv64:"ANDI [$]1," "BEQZ"
if a&0x1 != 0 {
return 1
}
@@ -137,25 +137,25 @@ func bitsSetU64(a, b uint64) (n uint64) {
// amd64:"BTSQ"
// arm64:"MOVD [$]1," "LSL" "ORR"
// loong64:"MOVV [$]1," "SLLV" "OR"
// riscv64:"ANDI" "SLL" "OR"
// riscv64:"ANDI [$]63," "MOV [$]1," "SLL " "OR "
n += b | (1 << (a & 63))
// amd64:"BTSQ [$]63,"
// arm64:"ORR [$]-9223372036854775808,"
// loong64:"MOVV [$]" "OR"
// riscv64:"MOV [$]" "OR "
// riscv64:"MOV [$]-9223372036854775808," "OR "
n += a | (1 << 63)
// amd64:"BTSQ [$]60,"
// arm64:"ORR [$]1152921504606846976,"
// loong64:"MOVV [$]" "OR"
// riscv64:"MOV [$]" "OR "
// riscv64:"MOV [$]1152921504606846976," "OR "
n += a | (1 << 60)
// amd64:"ORQ [$]1,"
// arm64:"ORR [$]1,"
// loong64:"OR [$]1,"
// riscv64:"ORI"
// riscv64:"ORI [$]1,"
n += a | (1 << 0)
return n
@@ -165,25 +165,25 @@ func bitsClearU64(a, b uint64) (n uint64) {
// amd64:"BTRQ"
// arm64:"MOVD [$]1," "LSL" "BIC"
// loong64:"MOVV [$]1," "SLLV" "ANDN"
// riscv64:"ANDI" "SLL" "ANDN"
// riscv64:"ANDI [$]63," "MOV [$]1," "SLL " "ANDN"
n += b &^ (1 << (a & 63))
// amd64:"BTRQ [$]63,"
// arm64:"AND [$]9223372036854775807,"
// loong64:"MOVV [$]" "AND "
// riscv64:"MOV [$]" "AND "
// riscv64:"MOV [$]9223372036854775807," "AND "
n += a &^ (1 << 63)
// amd64:"BTRQ [$]60,"
// arm64:"AND [$]-1152921504606846977,"
// loong64:"MOVV [$]" "AND "
// riscv64:"MOV [$]" "AND "
// riscv64:"MOV [$]i64.efffffffffffffff" "AND "
n += a &^ (1 << 60)
// amd64:"ANDQ [$]-2"
// arm64:"AND [$]-2"
// loong64:"AND [$]-2"
// riscv64:"ANDI [$]-2"
// riscv64:"ANDI [$]-2,"
n += a &^ (1 << 0)
return n
@@ -209,19 +209,19 @@ func bitsFlipU64(a, b uint64) (n uint64) {
// amd64:"BTCQ"
// arm64:"MOVD [$]1," "LSL" "EOR"
// loong64:"MOVV [$]1," "SLLV" "XOR"
// riscv64:"ANDI" "SLL" "XOR "
// riscv64:"ANDI [$]63," "MOV [$]1," "SLL " "XOR "
n += b ^ (1 << (a & 63))
// amd64:"BTCQ [$]63,"
// arm64:"EOR [$]-9223372036854775808,"
// loong64:"MOVV [$]" "XOR"
// riscv64:"MOV [$]" "XOR "
// riscv64:"MOV [$]-9223372036854775808," "XOR "
n += a ^ (1 << 63)
// amd64:"BTCQ [$]60,"
// arm64:"EOR [$]1152921504606846976,"
// loong64:"MOVV [$]" "XOR"
// riscv64:"MOV [$]" "XOR "
// riscv64:"MOV [$]1152921504606846976," "XOR "
n += a ^ (1 << 60)
// amd64:"XORQ [$]1,"
@@ -241,21 +241,21 @@ func bitsCheckConstShiftLeftU32(a uint32) (n int) {
// amd64:"BTL [$]31,"
// arm64:"TBNZ [$]31,"
// loong64:"AND [$]" "MOVWU" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]2147483648," "AND " "BNEZ"
if a&(1<<31) != 0 {
return 1
}
// amd64:"BTL [$]28,"
// arm64:"TBNZ [$]28,"
// loong64:"AND [$]" "BNE"
// riscv64:"ANDI" "BNEZ"
// riscv64:"ANDI [$]268435456," "BNEZ"
if a&(1<<28) != 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ [$]0,"
// loong64:"AND [$]" "BEQ"
// riscv64:"ANDI" "BEQZ"
// riscv64:"ANDI [$]1," "BEQZ"
if a&(1<<0) != 0 {
return 1
}
@@ -266,49 +266,49 @@ func bitsCheckConstRightShiftU32(a [8]uint32) (n int) {
// amd64:"BTL [$]31,"
// arm64:"UBFX [$]31," "CBNZW"
// loong64:"SRL [$]31," "AND [$]1," "BNE"
// riscv64:"SRLI" "ANDI" "BNEZ"
// riscv64:"SRLIW [$]31," "ANDI [$]1," "BNEZ"
if (a[0]>>31)&1 != 0 {
return 1
}
// amd64:"BTL [$]31,"
// arm64:"UBFX [$]31," "CBNZW"
// loong64:"SRL [$]31," "MOVWU" "BNE"
// riscv64:"SRLI" "BNEZ"
// riscv64:"SRLIW [$]31," "BNEZ" -"ANDI"
if a[1]>>31 != 0 {
return 1
}
// amd64:"BTL [$]31,"
// arm64:"UBFX [$]31," "CBZW"
// loong64:"SRL [$]31," "MOVWU" "BEQ"
// riscv64:"SRLI" "BEQZ"
// riscv64:"SRLIW [$]31," "BEQZ" -"ANDI"
if a[2]>>31 == 0 {
return 1
}
// amd64:"BTL [$]28,"
// arm64:"UBFX [$]28," "TBZ"
// loong64:"SRL [$]28," "AND [$]1," "BEQ"
// riscv64:"SRLI" "ANDI" "BEQZ"
// riscv64:"SRLIW [$]28," "ANDI [$]1," "BEQZ"
if (a[3]>>28)&1 == 0 {
return 1
}
// amd64:"BTL [$]1,"
// arm64:"UBFX [$]1," "TBZ"
// loong64:"SRL [$]1," "AND [$]1," "BEQ"
// riscv64:"SRLI" "ANDI" "BEQZ"
// riscv64:"SRLIW [$]1," "ANDI [$]1," "BEQZ"
if (a[4]>>1)&1 == 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ" -"UBFX" -"SRL"
// loong64:"AND [$]1," "BEQ" -"SRL [$]"
// riscv64:"ANDI" "BEQZ" -"SRLI "
// riscv64:"ANDI [$]1," "BEQZ" -"SRLI "
if (a[5]>>0)&1 == 0 {
return 1
}
// amd64:"BTL [$]7,"
// arm64:"UBFX [$]5," "TBNZ"
// loong64:"SRL [$]5," "AND [$]4," "BNE"
// riscv64:"SRLI" "ANDI" "BNEZ"
// riscv64:"SRLIW [$]5," "ANDI [$]4," "BNEZ"
if (a[6]>>5)&4 == 0 {
return 1
}
@@ -319,7 +319,7 @@ func bitsCheckVarU32(a, b uint32) (n int) {
// amd64:"BTL"
// arm64:"AND [$]31," "MOVD [$]1," "LSL" "TSTW"
// loong64:"MOVV [$]1," "SLL R" "AND R" "MOVWU" "BNE"
// riscv64:"ANDI [$]31," "SLL " "AND "
// riscv64:"ANDI [$]31," "MOV [$]1," "SLL " "AND "
if a&(1<<(b&31)) != 0 {
return 1
}
@@ -337,21 +337,21 @@ func bitsCheckMaskU32(a uint32) (n int) {
// amd64:"BTL [$]31,"
// arm64:"TBNZ [$]31,"
// loong64:"AND [$]" "MOVWU" "BNE"
// riscv64:"MOV [$]" "AND" "BNEZ"
// riscv64:"MOV [$]2147483648," "AND " "BNEZ"
if a&0x80000000 != 0 {
return 1
}
// amd64:"BTL [$]27,"
// arm64:"TBNZ [$]27,"
// loong64:"AND [$]" "BNE"
// riscv64:"ANDI" "BNEZ"
// riscv64:"ANDI [$]134217728," "BNEZ"
if a&0x8000000 != 0 {
return 1
}
// amd64:"BTL [$]0,"
// arm64:"TBZ [$]0,"
// loong64:"AND [$]1," "BEQ"
// riscv64:"ANDI" "BEQZ"
// riscv64:"ANDI [$]1," "BEQZ"
if a&0x1 != 0 {
return 1
}
@@ -362,7 +362,7 @@ func bitsSetU32(a, b uint32) (n uint32) {
// amd64:"BTSL"
// arm64:"AND [$]31," "MOVD [$]1," "LSL" "ORR"
// loong64:"MOVV [$]1," "SLL " "OR "
// riscv64:"ANDI" "SLL" "OR"
// riscv64:"ANDI [$]31," "MOV [$]1," "SLL " "OR "
n += b | (1 << (a & 31))
// amd64:"ORL [$]-2147483648,"
@@ -390,7 +390,7 @@ func bitsClearU32(a, b uint32) (n uint32) {
// amd64:"BTRL"
// arm64:"AND [$]31," "MOVD [$]1," "LSL" "BIC"
// loong64:"MOVV [$]1," "SLL R" "ANDN"
// riscv64:"ANDI" "SLL" "ANDN"
// riscv64:"ANDI [$]31," "MOV [$]1," "SLL " "ANDN"
n += b &^ (1 << (a & 31))
// amd64:"ANDL [$]2147483647,"
@@ -418,7 +418,7 @@ func bitsFlipU32(a, b uint32) (n uint32) {
// amd64:"BTCL"
// arm64:"AND [$]31," "MOVD [$]1," "LSL" "EOR"
// loong64:"MOVV [$]1," "SLL R" "XOR"
// riscv64:"ANDI" "SLL" "XOR "
// riscv64:"ANDI [$]31," "MOV [$]1," "SLL " "XOR "
n += b ^ (1 << (a & 31))
// amd64:"XORL [$]-2147483648,"
@@ -489,22 +489,22 @@ func bitsAndNot(x, y uint32) uint32 {
func bitsXorNot(x, y, z uint32, a []uint32, n, m uint64) uint64 {
// arm64:`EON `,-`EOR`,-`MVN`
// loong64:"NOR" "XOR"
// riscv64:"XNOR " -"MOV [$]" -"XOR"
// riscv64:"XNOR " -"MOV [$]" -"XOR "
a[0] = x ^ (y ^ 0xffffffff)
// arm64:`EON `,-`EOR`,-`MVN`
// loong64:"XOR" "NOR"
// riscv64:"XNOR" -"XOR"
// riscv64:"XNOR" -"XOR "
a[1] = ^(y ^ z)
// arm64:`EON `,-`XOR`
// loong64:"NOR" "XOR"
// riscv64:"XNOR" -"XOR" -"NOT"
// riscv64:"XNOR" -"XOR " -"NOT"
a[2] = x ^ ^z
// arm64:`EON `,-`EOR`,-`MVN`
// loong64:"NOR" "XOR"
// riscv64:"XNOR" -"MOV [$]" -"XOR"
// riscv64:"XNOR" -"MOV [$]" -"XOR "
return n ^ (m ^ 0xffffffffffffffff)
}